Type Alias R

pub type R = R<DIN_MODE_SPEC>;

Register DIN_MODE reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn din0_mode(&self) -> DIN0_MODE_R

Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din1_mode(&self) -> DIN1_MODE_R

Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din2_mode(&self) -> DIN2_MODE_R

Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din3_mode(&self) -> DIN3_MODE_R

Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din4_mode(&self) -> DIN4_MODE_R

Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din5_mode(&self) -> DIN5_MODE_R

Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din6_mode(&self) -> DIN6_MODE_R

Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din7_mode(&self) -> DIN7_MODE_R

Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn timing_clk_ena(&self) -> TIMING_CLK_ENA_R

Bit 24 - 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state.