1#[doc = "Register `DIN_NUM` reader"]
2pub type R = crate::R<DIN_NUM_SPEC>;
3#[doc = "Register `DIN_NUM` writer"]
4pub type W = crate::W<DIN_NUM_SPEC>;
5#[doc = "Field `DIN0_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
6pub type DIN0_NUM_R = crate::FieldReader;
7#[doc = "Field `DIN0_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
8pub type DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DIN1_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
10pub type DIN1_NUM_R = crate::FieldReader;
11#[doc = "Field `DIN1_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
12pub type DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DIN2_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
14pub type DIN2_NUM_R = crate::FieldReader;
15#[doc = "Field `DIN2_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
16pub type DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `DIN3_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
18pub type DIN3_NUM_R = crate::FieldReader;
19#[doc = "Field `DIN3_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
20pub type DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `DIN4_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
22pub type DIN4_NUM_R = crate::FieldReader;
23#[doc = "Field `DIN4_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
24pub type DIN4_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `DIN5_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
26pub type DIN5_NUM_R = crate::FieldReader;
27#[doc = "Field `DIN5_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
28pub type DIN5_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `DIN6_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
30pub type DIN6_NUM_R = crate::FieldReader;
31#[doc = "Field `DIN6_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
32pub type DIN6_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `DIN7_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
34pub type DIN7_NUM_R = crate::FieldReader;
35#[doc = "Field `DIN7_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
36pub type DIN7_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37impl R {
38 #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
39 #[inline(always)]
40 pub fn din0_num(&self) -> DIN0_NUM_R {
41 DIN0_NUM_R::new((self.bits & 3) as u8)
42 }
43 #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
44 #[inline(always)]
45 pub fn din1_num(&self) -> DIN1_NUM_R {
46 DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8)
47 }
48 #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
49 #[inline(always)]
50 pub fn din2_num(&self) -> DIN2_NUM_R {
51 DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8)
52 }
53 #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
54 #[inline(always)]
55 pub fn din3_num(&self) -> DIN3_NUM_R {
56 DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8)
57 }
58 #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
59 #[inline(always)]
60 pub fn din4_num(&self) -> DIN4_NUM_R {
61 DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8)
62 }
63 #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
64 #[inline(always)]
65 pub fn din5_num(&self) -> DIN5_NUM_R {
66 DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8)
67 }
68 #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
69 #[inline(always)]
70 pub fn din6_num(&self) -> DIN6_NUM_R {
71 DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8)
72 }
73 #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
74 #[inline(always)]
75 pub fn din7_num(&self) -> DIN7_NUM_R {
76 DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("DIN_NUM")
83 .field("din0_num", &self.din0_num())
84 .field("din1_num", &self.din1_num())
85 .field("din2_num", &self.din2_num())
86 .field("din3_num", &self.din3_num())
87 .field("din4_num", &self.din4_num())
88 .field("din5_num", &self.din5_num())
89 .field("din6_num", &self.din6_num())
90 .field("din7_num", &self.din7_num())
91 .finish()
92 }
93}
94impl W {
95 #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
96 #[inline(always)]
97 pub fn din0_num(&mut self) -> DIN0_NUM_W<DIN_NUM_SPEC> {
98 DIN0_NUM_W::new(self, 0)
99 }
100 #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
101 #[inline(always)]
102 pub fn din1_num(&mut self) -> DIN1_NUM_W<DIN_NUM_SPEC> {
103 DIN1_NUM_W::new(self, 2)
104 }
105 #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
106 #[inline(always)]
107 pub fn din2_num(&mut self) -> DIN2_NUM_W<DIN_NUM_SPEC> {
108 DIN2_NUM_W::new(self, 4)
109 }
110 #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
111 #[inline(always)]
112 pub fn din3_num(&mut self) -> DIN3_NUM_W<DIN_NUM_SPEC> {
113 DIN3_NUM_W::new(self, 6)
114 }
115 #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
116 #[inline(always)]
117 pub fn din4_num(&mut self) -> DIN4_NUM_W<DIN_NUM_SPEC> {
118 DIN4_NUM_W::new(self, 8)
119 }
120 #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
121 #[inline(always)]
122 pub fn din5_num(&mut self) -> DIN5_NUM_W<DIN_NUM_SPEC> {
123 DIN5_NUM_W::new(self, 10)
124 }
125 #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
126 #[inline(always)]
127 pub fn din6_num(&mut self) -> DIN6_NUM_W<DIN_NUM_SPEC> {
128 DIN6_NUM_W::new(self, 12)
129 }
130 #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
131 #[inline(always)]
132 pub fn din7_num(&mut self) -> DIN7_NUM_W<DIN_NUM_SPEC> {
133 DIN7_NUM_W::new(self, 14)
134 }
135}
136#[doc = "SPI input delay number configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`din_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`din_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct DIN_NUM_SPEC;
138impl crate::RegisterSpec for DIN_NUM_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`din_num::R`](R) reader structure"]
142impl crate::Readable for DIN_NUM_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`din_num::W`](W) writer structure"]
144impl crate::Writable for DIN_NUM_SPEC {
145 type Safety = crate::Unsafe;
146}
147#[doc = "`reset()` method sets DIN_NUM to value 0"]
148impl crate::Resettable for DIN_NUM_SPEC {}