1#[doc = "Register `PD_CONF` reader"]
2pub type R = crate::R<PD_CONF_SPEC>;
3#[doc = "Register `PD_CONF` writer"]
4pub type W = crate::W<PD_CONF_SPEC>;
5#[doc = "Field `FIFO_FORCE_PD` reader - Force FIFO power-down."]
6pub type FIFO_FORCE_PD_R = crate::BitReader;
7#[doc = "Field `FIFO_FORCE_PD` writer - Force FIFO power-down."]
8pub type FIFO_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FIFO_FORCE_PU` reader - Force FIFO power-up."]
10pub type FIFO_FORCE_PU_R = crate::BitReader;
11#[doc = "Field `FIFO_FORCE_PU` writer - Force FIFO power-up."]
12pub type FIFO_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PLC_MEM_FORCE_PD` reader - Force I2S memory power-down."]
14pub type PLC_MEM_FORCE_PD_R = crate::BitReader;
15#[doc = "Field `PLC_MEM_FORCE_PD` writer - Force I2S memory power-down."]
16pub type PLC_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PLC_MEM_FORCE_PU` reader - Force I2S memory power-up."]
18pub type PLC_MEM_FORCE_PU_R = crate::BitReader;
19#[doc = "Field `PLC_MEM_FORCE_PU` writer - Force I2S memory power-up."]
20pub type PLC_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DMA_RAM_FORCE_PD` reader - Force DMA FIFO power-down."]
22pub type DMA_RAM_FORCE_PD_R = crate::BitReader;
23#[doc = "Field `DMA_RAM_FORCE_PD` writer - Force DMA FIFO power-down."]
24pub type DMA_RAM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DMA_RAM_FORCE_PU` reader - Force DMA FIFO power-up."]
26pub type DMA_RAM_FORCE_PU_R = crate::BitReader;
27#[doc = "Field `DMA_RAM_FORCE_PU` writer - Force DMA FIFO power-up."]
28pub type DMA_RAM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DMA_RAM_CLK_FO` reader - Set this bit to force on DMA RAM clock."]
30pub type DMA_RAM_CLK_FO_R = crate::BitReader;
31#[doc = "Field `DMA_RAM_CLK_FO` writer - Set this bit to force on DMA RAM clock."]
32pub type DMA_RAM_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bit 0 - Force FIFO power-down."]
35 #[inline(always)]
36 pub fn fifo_force_pd(&self) -> FIFO_FORCE_PD_R {
37 FIFO_FORCE_PD_R::new((self.bits & 1) != 0)
38 }
39 #[doc = "Bit 1 - Force FIFO power-up."]
40 #[inline(always)]
41 pub fn fifo_force_pu(&self) -> FIFO_FORCE_PU_R {
42 FIFO_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0)
43 }
44 #[doc = "Bit 2 - Force I2S memory power-down."]
45 #[inline(always)]
46 pub fn plc_mem_force_pd(&self) -> PLC_MEM_FORCE_PD_R {
47 PLC_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0)
48 }
49 #[doc = "Bit 3 - Force I2S memory power-up."]
50 #[inline(always)]
51 pub fn plc_mem_force_pu(&self) -> PLC_MEM_FORCE_PU_R {
52 PLC_MEM_FORCE_PU_R::new(((self.bits >> 3) & 1) != 0)
53 }
54 #[doc = "Bit 4 - Force DMA FIFO power-down."]
55 #[inline(always)]
56 pub fn dma_ram_force_pd(&self) -> DMA_RAM_FORCE_PD_R {
57 DMA_RAM_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0)
58 }
59 #[doc = "Bit 5 - Force DMA FIFO power-up."]
60 #[inline(always)]
61 pub fn dma_ram_force_pu(&self) -> DMA_RAM_FORCE_PU_R {
62 DMA_RAM_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0)
63 }
64 #[doc = "Bit 6 - Set this bit to force on DMA RAM clock."]
65 #[inline(always)]
66 pub fn dma_ram_clk_fo(&self) -> DMA_RAM_CLK_FO_R {
67 DMA_RAM_CLK_FO_R::new(((self.bits >> 6) & 1) != 0)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("PD_CONF")
74 .field("fifo_force_pd", &self.fifo_force_pd())
75 .field("fifo_force_pu", &self.fifo_force_pu())
76 .field("plc_mem_force_pd", &self.plc_mem_force_pd())
77 .field("plc_mem_force_pu", &self.plc_mem_force_pu())
78 .field("dma_ram_force_pd", &self.dma_ram_force_pd())
79 .field("dma_ram_force_pu", &self.dma_ram_force_pu())
80 .field("dma_ram_clk_fo", &self.dma_ram_clk_fo())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bit 0 - Force FIFO power-down."]
86 #[inline(always)]
87 pub fn fifo_force_pd(&mut self) -> FIFO_FORCE_PD_W<PD_CONF_SPEC> {
88 FIFO_FORCE_PD_W::new(self, 0)
89 }
90 #[doc = "Bit 1 - Force FIFO power-up."]
91 #[inline(always)]
92 pub fn fifo_force_pu(&mut self) -> FIFO_FORCE_PU_W<PD_CONF_SPEC> {
93 FIFO_FORCE_PU_W::new(self, 1)
94 }
95 #[doc = "Bit 2 - Force I2S memory power-down."]
96 #[inline(always)]
97 pub fn plc_mem_force_pd(&mut self) -> PLC_MEM_FORCE_PD_W<PD_CONF_SPEC> {
98 PLC_MEM_FORCE_PD_W::new(self, 2)
99 }
100 #[doc = "Bit 3 - Force I2S memory power-up."]
101 #[inline(always)]
102 pub fn plc_mem_force_pu(&mut self) -> PLC_MEM_FORCE_PU_W<PD_CONF_SPEC> {
103 PLC_MEM_FORCE_PU_W::new(self, 3)
104 }
105 #[doc = "Bit 4 - Force DMA FIFO power-down."]
106 #[inline(always)]
107 pub fn dma_ram_force_pd(&mut self) -> DMA_RAM_FORCE_PD_W<PD_CONF_SPEC> {
108 DMA_RAM_FORCE_PD_W::new(self, 4)
109 }
110 #[doc = "Bit 5 - Force DMA FIFO power-up."]
111 #[inline(always)]
112 pub fn dma_ram_force_pu(&mut self) -> DMA_RAM_FORCE_PU_W<PD_CONF_SPEC> {
113 DMA_RAM_FORCE_PU_W::new(self, 5)
114 }
115 #[doc = "Bit 6 - Set this bit to force on DMA RAM clock."]
116 #[inline(always)]
117 pub fn dma_ram_clk_fo(&mut self) -> DMA_RAM_CLK_FO_W<PD_CONF_SPEC> {
118 DMA_RAM_CLK_FO_W::new(self, 6)
119 }
120}
121#[doc = "I2S power-down configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct PD_CONF_SPEC;
123impl crate::RegisterSpec for PD_CONF_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`pd_conf::R`](R) reader structure"]
127impl crate::Readable for PD_CONF_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`pd_conf::W`](W) writer structure"]
129impl crate::Writable for PD_CONF_SPEC {
130 type Safety = crate::Unsafe;
131}
132#[doc = "`reset()` method sets PD_CONF to value 0x2a"]
133impl crate::Resettable for PD_CONF_SPEC {
134 const RESET_VALUE: u32 = 0x2a;
135}