esp32s2/extmem/
pro_icache_ctrl.rs

1#[doc = "Register `PRO_ICACHE_CTRL` reader"]
2pub type R = crate::R<PRO_ICACHE_CTRL_SPEC>;
3#[doc = "Register `PRO_ICACHE_CTRL` writer"]
4pub type W = crate::W<PRO_ICACHE_CTRL_SPEC>;
5#[doc = "Field `PRO_ICACHE_ENABLE` reader - The bit is used to activate the data cache. 0: disable, 1: enable"]
6pub type PRO_ICACHE_ENABLE_R = crate::BitReader;
7#[doc = "Field `PRO_ICACHE_ENABLE` writer - The bit is used to activate the data cache. 0: disable, 1: enable"]
8pub type PRO_ICACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_ICACHE_SETSIZE_MODE` reader - The bit is used to configure cache memory size.0: 8KB, 1: 16KB"]
10pub type PRO_ICACHE_SETSIZE_MODE_R = crate::BitReader;
11#[doc = "Field `PRO_ICACHE_SETSIZE_MODE` writer - The bit is used to configure cache memory size.0: 8KB, 1: 16KB"]
12pub type PRO_ICACHE_SETSIZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_ICACHE_BLOCKSIZE_MODE` reader - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
14pub type PRO_ICACHE_BLOCKSIZE_MODE_R = crate::BitReader;
15#[doc = "Field `PRO_ICACHE_BLOCKSIZE_MODE` writer - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
16pub type PRO_ICACHE_BLOCKSIZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PRO_ICACHE_INVALIDATE_ENA` reader - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
18pub type PRO_ICACHE_INVALIDATE_ENA_R = crate::BitReader;
19#[doc = "Field `PRO_ICACHE_INVALIDATE_ENA` writer - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
20pub type PRO_ICACHE_INVALIDATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PRO_ICACHE_INVALIDATE_DONE` reader - The bit is used to indicate invalidate operation is finished."]
22pub type PRO_ICACHE_INVALIDATE_DONE_R = crate::BitReader;
23#[doc = "Field `PRO_ICACHE_LOCK0_EN` reader - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG."]
24pub type PRO_ICACHE_LOCK0_EN_R = crate::BitReader;
25#[doc = "Field `PRO_ICACHE_LOCK0_EN` writer - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG."]
26pub type PRO_ICACHE_LOCK0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `PRO_ICACHE_LOCK1_EN` reader - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG."]
28pub type PRO_ICACHE_LOCK1_EN_R = crate::BitReader;
29#[doc = "Field `PRO_ICACHE_LOCK1_EN` writer - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG."]
30pub type PRO_ICACHE_LOCK1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `PRO_ICACHE_AUTOLOAD_ENA` reader - The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable."]
32pub type PRO_ICACHE_AUTOLOAD_ENA_R = crate::BitReader;
33#[doc = "Field `PRO_ICACHE_AUTOLOAD_ENA` writer - The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable."]
34pub type PRO_ICACHE_AUTOLOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `PRO_ICACHE_AUTOLOAD_DONE` reader - The bit is used to indicate conditional-preload operation is finished."]
36pub type PRO_ICACHE_AUTOLOAD_DONE_R = crate::BitReader;
37#[doc = "Field `PRO_ICACHE_PRELOAD_ENA` reader - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
38pub type PRO_ICACHE_PRELOAD_ENA_R = crate::BitReader;
39#[doc = "Field `PRO_ICACHE_PRELOAD_ENA` writer - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
40pub type PRO_ICACHE_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PRO_ICACHE_PRELOAD_DONE` reader - The bit is used to indicate preload operation is finished."]
42pub type PRO_ICACHE_PRELOAD_DONE_R = crate::BitReader;
43#[doc = "Field `PRO_ICACHE_UNLOCK_ENA` reader - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
44pub type PRO_ICACHE_UNLOCK_ENA_R = crate::BitReader;
45#[doc = "Field `PRO_ICACHE_UNLOCK_ENA` writer - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
46pub type PRO_ICACHE_UNLOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `PRO_ICACHE_UNLOCK_DONE` reader - The bit is used to indicate unlock operation is finished."]
48pub type PRO_ICACHE_UNLOCK_DONE_R = crate::BitReader;
49#[doc = "Field `PRO_ICACHE_LOCK_ENA` reader - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
50pub type PRO_ICACHE_LOCK_ENA_R = crate::BitReader;
51#[doc = "Field `PRO_ICACHE_LOCK_ENA` writer - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
52pub type PRO_ICACHE_LOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `PRO_ICACHE_LOCK_DONE` reader - The bit is used to indicate lock operation is finished."]
54pub type PRO_ICACHE_LOCK_DONE_R = crate::BitReader;
55impl R {
56    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
57    #[inline(always)]
58    pub fn pro_icache_enable(&self) -> PRO_ICACHE_ENABLE_R {
59        PRO_ICACHE_ENABLE_R::new((self.bits & 1) != 0)
60    }
61    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 8KB, 1: 16KB"]
62    #[inline(always)]
63    pub fn pro_icache_setsize_mode(&self) -> PRO_ICACHE_SETSIZE_MODE_R {
64        PRO_ICACHE_SETSIZE_MODE_R::new(((self.bits >> 2) & 1) != 0)
65    }
66    #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
67    #[inline(always)]
68    pub fn pro_icache_blocksize_mode(&self) -> PRO_ICACHE_BLOCKSIZE_MODE_R {
69        PRO_ICACHE_BLOCKSIZE_MODE_R::new(((self.bits >> 3) & 1) != 0)
70    }
71    #[doc = "Bit 8 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
72    #[inline(always)]
73    pub fn pro_icache_invalidate_ena(&self) -> PRO_ICACHE_INVALIDATE_ENA_R {
74        PRO_ICACHE_INVALIDATE_ENA_R::new(((self.bits >> 8) & 1) != 0)
75    }
76    #[doc = "Bit 9 - The bit is used to indicate invalidate operation is finished."]
77    #[inline(always)]
78    pub fn pro_icache_invalidate_done(&self) -> PRO_ICACHE_INVALIDATE_DONE_R {
79        PRO_ICACHE_INVALIDATE_DONE_R::new(((self.bits >> 9) & 1) != 0)
80    }
81    #[doc = "Bit 14 - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG."]
82    #[inline(always)]
83    pub fn pro_icache_lock0_en(&self) -> PRO_ICACHE_LOCK0_EN_R {
84        PRO_ICACHE_LOCK0_EN_R::new(((self.bits >> 14) & 1) != 0)
85    }
86    #[doc = "Bit 15 - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG."]
87    #[inline(always)]
88    pub fn pro_icache_lock1_en(&self) -> PRO_ICACHE_LOCK1_EN_R {
89        PRO_ICACHE_LOCK1_EN_R::new(((self.bits >> 15) & 1) != 0)
90    }
91    #[doc = "Bit 18 - The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable."]
92    #[inline(always)]
93    pub fn pro_icache_autoload_ena(&self) -> PRO_ICACHE_AUTOLOAD_ENA_R {
94        PRO_ICACHE_AUTOLOAD_ENA_R::new(((self.bits >> 18) & 1) != 0)
95    }
96    #[doc = "Bit 19 - The bit is used to indicate conditional-preload operation is finished."]
97    #[inline(always)]
98    pub fn pro_icache_autoload_done(&self) -> PRO_ICACHE_AUTOLOAD_DONE_R {
99        PRO_ICACHE_AUTOLOAD_DONE_R::new(((self.bits >> 19) & 1) != 0)
100    }
101    #[doc = "Bit 20 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
102    #[inline(always)]
103    pub fn pro_icache_preload_ena(&self) -> PRO_ICACHE_PRELOAD_ENA_R {
104        PRO_ICACHE_PRELOAD_ENA_R::new(((self.bits >> 20) & 1) != 0)
105    }
106    #[doc = "Bit 21 - The bit is used to indicate preload operation is finished."]
107    #[inline(always)]
108    pub fn pro_icache_preload_done(&self) -> PRO_ICACHE_PRELOAD_DONE_R {
109        PRO_ICACHE_PRELOAD_DONE_R::new(((self.bits >> 21) & 1) != 0)
110    }
111    #[doc = "Bit 22 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
112    #[inline(always)]
113    pub fn pro_icache_unlock_ena(&self) -> PRO_ICACHE_UNLOCK_ENA_R {
114        PRO_ICACHE_UNLOCK_ENA_R::new(((self.bits >> 22) & 1) != 0)
115    }
116    #[doc = "Bit 23 - The bit is used to indicate unlock operation is finished."]
117    #[inline(always)]
118    pub fn pro_icache_unlock_done(&self) -> PRO_ICACHE_UNLOCK_DONE_R {
119        PRO_ICACHE_UNLOCK_DONE_R::new(((self.bits >> 23) & 1) != 0)
120    }
121    #[doc = "Bit 24 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
122    #[inline(always)]
123    pub fn pro_icache_lock_ena(&self) -> PRO_ICACHE_LOCK_ENA_R {
124        PRO_ICACHE_LOCK_ENA_R::new(((self.bits >> 24) & 1) != 0)
125    }
126    #[doc = "Bit 25 - The bit is used to indicate lock operation is finished."]
127    #[inline(always)]
128    pub fn pro_icache_lock_done(&self) -> PRO_ICACHE_LOCK_DONE_R {
129        PRO_ICACHE_LOCK_DONE_R::new(((self.bits >> 25) & 1) != 0)
130    }
131}
132#[cfg(feature = "impl-register-debug")]
133impl core::fmt::Debug for R {
134    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
135        f.debug_struct("PRO_ICACHE_CTRL")
136            .field("pro_icache_enable", &self.pro_icache_enable())
137            .field("pro_icache_setsize_mode", &self.pro_icache_setsize_mode())
138            .field(
139                "pro_icache_blocksize_mode",
140                &self.pro_icache_blocksize_mode(),
141            )
142            .field(
143                "pro_icache_invalidate_ena",
144                &self.pro_icache_invalidate_ena(),
145            )
146            .field(
147                "pro_icache_invalidate_done",
148                &self.pro_icache_invalidate_done(),
149            )
150            .field("pro_icache_lock0_en", &self.pro_icache_lock0_en())
151            .field("pro_icache_lock1_en", &self.pro_icache_lock1_en())
152            .field("pro_icache_autoload_ena", &self.pro_icache_autoload_ena())
153            .field("pro_icache_autoload_done", &self.pro_icache_autoload_done())
154            .field("pro_icache_preload_ena", &self.pro_icache_preload_ena())
155            .field("pro_icache_preload_done", &self.pro_icache_preload_done())
156            .field("pro_icache_unlock_ena", &self.pro_icache_unlock_ena())
157            .field("pro_icache_unlock_done", &self.pro_icache_unlock_done())
158            .field("pro_icache_lock_ena", &self.pro_icache_lock_ena())
159            .field("pro_icache_lock_done", &self.pro_icache_lock_done())
160            .finish()
161    }
162}
163impl W {
164    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
165    #[inline(always)]
166    pub fn pro_icache_enable(&mut self) -> PRO_ICACHE_ENABLE_W<PRO_ICACHE_CTRL_SPEC> {
167        PRO_ICACHE_ENABLE_W::new(self, 0)
168    }
169    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 8KB, 1: 16KB"]
170    #[inline(always)]
171    pub fn pro_icache_setsize_mode(&mut self) -> PRO_ICACHE_SETSIZE_MODE_W<PRO_ICACHE_CTRL_SPEC> {
172        PRO_ICACHE_SETSIZE_MODE_W::new(self, 2)
173    }
174    #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
175    #[inline(always)]
176    pub fn pro_icache_blocksize_mode(
177        &mut self,
178    ) -> PRO_ICACHE_BLOCKSIZE_MODE_W<PRO_ICACHE_CTRL_SPEC> {
179        PRO_ICACHE_BLOCKSIZE_MODE_W::new(self, 3)
180    }
181    #[doc = "Bit 8 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
182    #[inline(always)]
183    pub fn pro_icache_invalidate_ena(
184        &mut self,
185    ) -> PRO_ICACHE_INVALIDATE_ENA_W<PRO_ICACHE_CTRL_SPEC> {
186        PRO_ICACHE_INVALIDATE_ENA_W::new(self, 8)
187    }
188    #[doc = "Bit 14 - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG."]
189    #[inline(always)]
190    pub fn pro_icache_lock0_en(&mut self) -> PRO_ICACHE_LOCK0_EN_W<PRO_ICACHE_CTRL_SPEC> {
191        PRO_ICACHE_LOCK0_EN_W::new(self, 14)
192    }
193    #[doc = "Bit 15 - The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG."]
194    #[inline(always)]
195    pub fn pro_icache_lock1_en(&mut self) -> PRO_ICACHE_LOCK1_EN_W<PRO_ICACHE_CTRL_SPEC> {
196        PRO_ICACHE_LOCK1_EN_W::new(self, 15)
197    }
198    #[doc = "Bit 18 - The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable."]
199    #[inline(always)]
200    pub fn pro_icache_autoload_ena(&mut self) -> PRO_ICACHE_AUTOLOAD_ENA_W<PRO_ICACHE_CTRL_SPEC> {
201        PRO_ICACHE_AUTOLOAD_ENA_W::new(self, 18)
202    }
203    #[doc = "Bit 20 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
204    #[inline(always)]
205    pub fn pro_icache_preload_ena(&mut self) -> PRO_ICACHE_PRELOAD_ENA_W<PRO_ICACHE_CTRL_SPEC> {
206        PRO_ICACHE_PRELOAD_ENA_W::new(self, 20)
207    }
208    #[doc = "Bit 22 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done."]
209    #[inline(always)]
210    pub fn pro_icache_unlock_ena(&mut self) -> PRO_ICACHE_UNLOCK_ENA_W<PRO_ICACHE_CTRL_SPEC> {
211        PRO_ICACHE_UNLOCK_ENA_W::new(self, 22)
212    }
213    #[doc = "Bit 24 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
214    #[inline(always)]
215    pub fn pro_icache_lock_ena(&mut self) -> PRO_ICACHE_LOCK_ENA_W<PRO_ICACHE_CTRL_SPEC> {
216        PRO_ICACHE_LOCK_ENA_W::new(self, 24)
217    }
218}
219#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
220pub struct PRO_ICACHE_CTRL_SPEC;
221impl crate::RegisterSpec for PRO_ICACHE_CTRL_SPEC {
222    type Ux = u32;
223}
224#[doc = "`read()` method returns [`pro_icache_ctrl::R`](R) reader structure"]
225impl crate::Readable for PRO_ICACHE_CTRL_SPEC {}
226#[doc = "`write(|w| ..)` method takes [`pro_icache_ctrl::W`](W) writer structure"]
227impl crate::Writable for PRO_ICACHE_CTRL_SPEC {
228    type Safety = crate::Unsafe;
229}
230#[doc = "`reset()` method sets PRO_ICACHE_CTRL to value 0x0100"]
231impl crate::Resettable for PRO_ICACHE_CTRL_SPEC {
232    const RESET_VALUE: u32 = 0x0100;
233}
esp32s2/extmem/pro_icache_ctrl.rs

esp32s2/extmem/
pro_icache_ctrl.rs
