esp32s2/extmem/
cache_sync_int_ctrl.rs

1#[doc = "Register `CACHE_SYNC_INT_CTRL` reader"]
2pub type R = crate::R<CACHE_SYNC_INT_CTRL_SPEC>;
3#[doc = "Register `CACHE_SYNC_INT_CTRL` writer"]
4pub type W = crate::W<CACHE_SYNC_INT_CTRL_SPEC>;
5#[doc = "Field `PRO_ICACHE_SYNC_INT_ST` reader - The bit is used to indicate the interrupt by icache sync done."]
6pub type PRO_ICACHE_SYNC_INT_ST_R = crate::BitReader;
7#[doc = "Field `PRO_ICACHE_SYNC_INT_ENA` reader - The bit is used to enable the interrupt by icache sync done."]
8pub type PRO_ICACHE_SYNC_INT_ENA_R = crate::BitReader;
9#[doc = "Field `PRO_ICACHE_SYNC_INT_ENA` writer - The bit is used to enable the interrupt by icache sync done."]
10pub type PRO_ICACHE_SYNC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `PRO_ICACHE_SYNC_INT_CLR` writer - The bit is used to clear the interrupt by icache sync done."]
12pub type PRO_ICACHE_SYNC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_DCACHE_SYNC_INT_ST` reader - The bit is used to indicate the interrupt by dcache sync done."]
14pub type PRO_DCACHE_SYNC_INT_ST_R = crate::BitReader;
15#[doc = "Field `PRO_DCACHE_SYNC_INT_ENA` reader - The bit is used to enable the interrupt by dcache sync done."]
16pub type PRO_DCACHE_SYNC_INT_ENA_R = crate::BitReader;
17#[doc = "Field `PRO_DCACHE_SYNC_INT_ENA` writer - The bit is used to enable the interrupt by dcache sync done."]
18pub type PRO_DCACHE_SYNC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `PRO_DCACHE_SYNC_INT_CLR` writer - The bit is used to clear the interrupt by dcache sync done."]
20pub type PRO_DCACHE_SYNC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - The bit is used to indicate the interrupt by icache sync done."]
23    #[inline(always)]
24    pub fn pro_icache_sync_int_st(&self) -> PRO_ICACHE_SYNC_INT_ST_R {
25        PRO_ICACHE_SYNC_INT_ST_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
28    #[inline(always)]
29    pub fn pro_icache_sync_int_ena(&self) -> PRO_ICACHE_SYNC_INT_ENA_R {
30        PRO_ICACHE_SYNC_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 3 - The bit is used to indicate the interrupt by dcache sync done."]
33    #[inline(always)]
34    pub fn pro_dcache_sync_int_st(&self) -> PRO_DCACHE_SYNC_INT_ST_R {
35        PRO_DCACHE_SYNC_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
36    }
37    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache sync done."]
38    #[inline(always)]
39    pub fn pro_dcache_sync_int_ena(&self) -> PRO_DCACHE_SYNC_INT_ENA_R {
40        PRO_DCACHE_SYNC_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CACHE_SYNC_INT_CTRL")
47            .field("pro_icache_sync_int_st", &self.pro_icache_sync_int_st())
48            .field("pro_icache_sync_int_ena", &self.pro_icache_sync_int_ena())
49            .field("pro_dcache_sync_int_st", &self.pro_dcache_sync_int_st())
50            .field("pro_dcache_sync_int_ena", &self.pro_dcache_sync_int_ena())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
56    #[inline(always)]
57    pub fn pro_icache_sync_int_ena(
58        &mut self,
59    ) -> PRO_ICACHE_SYNC_INT_ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
60        PRO_ICACHE_SYNC_INT_ENA_W::new(self, 1)
61    }
62    #[doc = "Bit 2 - The bit is used to clear the interrupt by icache sync done."]
63    #[inline(always)]
64    pub fn pro_icache_sync_int_clr(
65        &mut self,
66    ) -> PRO_ICACHE_SYNC_INT_CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
67        PRO_ICACHE_SYNC_INT_CLR_W::new(self, 2)
68    }
69    #[doc = "Bit 4 - The bit is used to enable the interrupt by dcache sync done."]
70    #[inline(always)]
71    pub fn pro_dcache_sync_int_ena(
72        &mut self,
73    ) -> PRO_DCACHE_SYNC_INT_ENA_W<CACHE_SYNC_INT_CTRL_SPEC> {
74        PRO_DCACHE_SYNC_INT_ENA_W::new(self, 4)
75    }
76    #[doc = "Bit 5 - The bit is used to clear the interrupt by dcache sync done."]
77    #[inline(always)]
78    pub fn pro_dcache_sync_int_clr(
79        &mut self,
80    ) -> PRO_DCACHE_SYNC_INT_CLR_W<CACHE_SYNC_INT_CTRL_SPEC> {
81        PRO_DCACHE_SYNC_INT_CLR_W::new(self, 5)
82    }
83}
84#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sync_int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_sync_int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct CACHE_SYNC_INT_CTRL_SPEC;
86impl crate::RegisterSpec for CACHE_SYNC_INT_CTRL_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [`cache_sync_int_ctrl::R`](R) reader structure"]
90impl crate::Readable for CACHE_SYNC_INT_CTRL_SPEC {}
91#[doc = "`write(|w| ..)` method takes [`cache_sync_int_ctrl::W`](W) writer structure"]
92impl crate::Writable for CACHE_SYNC_INT_CTRL_SPEC {
93    type Safety = crate::Unsafe;
94}
95#[doc = "`reset()` method sets CACHE_SYNC_INT_CTRL to value 0"]
96impl crate::Resettable for CACHE_SYNC_INT_CTRL_SPEC {}
esp32s2/extmem/cache_sync_int_ctrl.rs

esp32s2/extmem/
cache_sync_int_ctrl.rs
