1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 filter_bank: [FILTER_BANK; 2],
6 _reserved1: [u8; 0x08],
7 rx_ctrl: RX_CTRL,
8 _reserved2: [u8; 0x04],
9 rx_dma_list: RX_DMA_LIST,
10 _reserved3: [u8; 0x44],
11 interface_rx_control: [INTERFACE_RX_CONTROL; 4],
12 _reserved4: [u8; 0x0710],
13 crypto_control: CRYPTO_CONTROL,
14 _reserved5: [u8; 0x0424],
15 mac_interrupt: MAC_INTERRUPT,
16 _reserved6: [u8; 0x58],
17 txq_state: TXQ_STATE,
18 _reserved7: [u8; 0x0c],
19 ctrl: CTRL,
20 _reserved8: [u8; 0x20],
21 tx_slot_config: [TX_SLOT_CONFIG; 5],
22 _reserved9: [u8; 0x0464],
23 plcp1: (),
24 _reserved10: [u8; 0x04],
25 plcp2: (),
26 _reserved11: [u8; 0x04],
27 ht_sig: (),
28 _reserved12: [u8; 0x04],
29 ht_unknown: (),
30 _reserved13: [u8; 0x04],
31 duration: (),
32 _reserved14: [u8; 0x08],
33 pmd: (),
34 _reserved15: [u8; 0x0280],
35 crypto_key_slot: [CRYPTO_KEY_SLOT; 25],
36 _reserved16: [u8; 0x0818],
37 mac_time: MAC_TIME,
38 _reserved17: [u8; 0x019c],
39 pwr_interrupt: PWR_INTERRUPT,
40}
41impl RegisterBlock {
42 #[doc = "0x00..0x80 - Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for four interfaces."]
43 #[inline(always)]
44 pub const fn filter_bank(&self, n: usize) -> &FILTER_BANK {
45 &self.filter_bank[n]
46 }
47 #[doc = "Iterator for array of:"]
48 #[doc = "0x00..0x80 - Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for four interfaces."]
49 #[inline(always)]
50 pub fn filter_bank_iter(&self) -> impl Iterator<Item = &FILTER_BANK> {
51 self.filter_bank.iter()
52 }
53 #[doc = "0x88 - Controls the reception of frames"]
54 #[inline(always)]
55 pub const fn rx_ctrl(&self) -> &RX_CTRL {
56 &self.rx_ctrl
57 }
58 #[doc = "0x90..0x9c - RX_DMA_LIST"]
59 #[inline(always)]
60 pub const fn rx_dma_list(&self) -> &RX_DMA_LIST {
61 &self.rx_dma_list
62 }
63 #[doc = "0xe0..0xf0 - Controls RX for an interface"]
64 #[inline(always)]
65 pub const fn interface_rx_control(&self, n: usize) -> &INTERFACE_RX_CONTROL {
66 &self.interface_rx_control[n]
67 }
68 #[doc = "Iterator for array of:"]
69 #[doc = "0xe0..0xf0 - Controls RX for an interface"]
70 #[inline(always)]
71 pub fn interface_rx_control_iter(&self) -> impl Iterator<Item = &INTERFACE_RX_CONTROL> {
72 self.interface_rx_control.iter()
73 }
74 #[doc = "0x800..0x818 - Control registers for hardware crypto"]
75 #[inline(always)]
76 pub const fn crypto_control(&self) -> &CRYPTO_CONTROL {
77 &self.crypto_control
78 }
79 #[doc = "0xc3c..0xc44 - Status and clear for the WIFI_MAC interrupt"]
80 #[inline(always)]
81 pub const fn mac_interrupt(&self) -> &MAC_INTERRUPT {
82 &self.mac_interrupt
83 }
84 #[doc = "0xc9c..0xcac - State of transmission queues"]
85 #[inline(always)]
86 pub const fn txq_state(&self) -> &TXQ_STATE {
87 &self.txq_state
88 }
89 #[doc = "0xcb8 - Exact name and meaning unknown, used for initializing the MAC"]
90 #[inline(always)]
91 pub const fn ctrl(&self) -> &CTRL {
92 &self.ctrl
93 }
94 #[doc = "0xcdc..0xd04 - Used to configure the TX slot."]
95 #[inline(always)]
96 pub const fn tx_slot_config(&self, n: usize) -> &TX_SLOT_CONFIG {
97 &self.tx_slot_config[n]
98 }
99 #[doc = "Iterator for array of:"]
100 #[doc = "0xcdc..0xd04 - Used to configure the TX slot."]
101 #[inline(always)]
102 pub fn tx_slot_config_iter(&self) -> impl Iterator<Item = &TX_SLOT_CONFIG> {
103 self.tx_slot_config.iter()
104 }
105 #[doc = "0x1168..0x117c - PLCP1"]
106 #[inline(always)]
107 pub const fn plcp1(&self, n: usize) -> &PLCP1 {
108 #[allow(clippy::no_effect)]
109 [(); 5][n];
110 unsafe {
111 &*core::ptr::from_ref(self)
112 .cast::<u8>()
113 .add(4456)
114 .add(60 * n)
115 .cast()
116 }
117 }
118 #[doc = "Iterator for array of:"]
119 #[doc = "0x1168..0x117c - PLCP1"]
120 #[inline(always)]
121 pub fn plcp1_iter(&self) -> impl Iterator<Item = &PLCP1> {
122 (0..5).map(move |n| unsafe {
123 &*core::ptr::from_ref(self)
124 .cast::<u8>()
125 .add(4456)
126 .add(60 * n)
127 .cast()
128 })
129 }
130 #[doc = "0x116c..0x1180 - PLCP2"]
131 #[inline(always)]
132 pub const fn plcp2(&self, n: usize) -> &PLCP2 {
133 #[allow(clippy::no_effect)]
134 [(); 5][n];
135 unsafe {
136 &*core::ptr::from_ref(self)
137 .cast::<u8>()
138 .add(4460)
139 .add(60 * n)
140 .cast()
141 }
142 }
143 #[doc = "Iterator for array of:"]
144 #[doc = "0x116c..0x1180 - PLCP2"]
145 #[inline(always)]
146 pub fn plcp2_iter(&self) -> impl Iterator<Item = &PLCP2> {
147 (0..5).map(move |n| unsafe {
148 &*core::ptr::from_ref(self)
149 .cast::<u8>()
150 .add(4460)
151 .add(60 * n)
152 .cast()
153 })
154 }
155 #[doc = "0x1170..0x1184 - HT-SIG field in HT preamble"]
156 #[inline(always)]
157 pub const fn ht_sig(&self, n: usize) -> &HT_SIG {
158 #[allow(clippy::no_effect)]
159 [(); 5][n];
160 unsafe {
161 &*core::ptr::from_ref(self)
162 .cast::<u8>()
163 .add(4464)
164 .add(60 * n)
165 .cast()
166 }
167 }
168 #[doc = "Iterator for array of:"]
169 #[doc = "0x1170..0x1184 - HT-SIG field in HT preamble"]
170 #[inline(always)]
171 pub fn ht_sig_iter(&self) -> impl Iterator<Item = &HT_SIG> {
172 (0..5).map(move |n| unsafe {
173 &*core::ptr::from_ref(self)
174 .cast::<u8>()
175 .add(4464)
176 .add(60 * n)
177 .cast()
178 })
179 }
180 #[doc = "0x1174..0x1188 - exact meaning and name unknown, related to HT"]
181 #[inline(always)]
182 pub const fn ht_unknown(&self, n: usize) -> &HT_UNKNOWN {
183 #[allow(clippy::no_effect)]
184 [(); 5][n];
185 unsafe {
186 &*core::ptr::from_ref(self)
187 .cast::<u8>()
188 .add(4468)
189 .add(60 * n)
190 .cast()
191 }
192 }
193 #[doc = "Iterator for array of:"]
194 #[doc = "0x1174..0x1188 - exact meaning and name unknown, related to HT"]
195 #[inline(always)]
196 pub fn ht_unknown_iter(&self) -> impl Iterator<Item = &HT_UNKNOWN> {
197 (0..5).map(move |n| unsafe {
198 &*core::ptr::from_ref(self)
199 .cast::<u8>()
200 .add(4468)
201 .add(60 * n)
202 .cast()
203 })
204 }
205 #[doc = "0x1178..0x118c - duration of the frame exchange"]
206 #[inline(always)]
207 pub const fn duration(&self, n: usize) -> &DURATION {
208 #[allow(clippy::no_effect)]
209 [(); 5][n];
210 unsafe {
211 &*core::ptr::from_ref(self)
212 .cast::<u8>()
213 .add(4472)
214 .add(60 * n)
215 .cast()
216 }
217 }
218 #[doc = "Iterator for array of:"]
219 #[doc = "0x1178..0x118c - duration of the frame exchange"]
220 #[inline(always)]
221 pub fn duration_iter(&self) -> impl Iterator<Item = &DURATION> {
222 (0..5).map(move |n| unsafe {
223 &*core::ptr::from_ref(self)
224 .cast::<u8>()
225 .add(4472)
226 .add(60 * n)
227 .cast()
228 })
229 }
230 #[doc = "0x1180..0x1194 - "]
231 #[inline(always)]
232 pub const fn pmd(&self, n: usize) -> &PMD {
233 #[allow(clippy::no_effect)]
234 [(); 5][n];
235 unsafe {
236 &*core::ptr::from_ref(self)
237 .cast::<u8>()
238 .add(4480)
239 .add(60 * n)
240 .cast()
241 }
242 }
243 #[doc = "Iterator for array of:"]
244 #[doc = "0x1180..0x1194 - "]
245 #[inline(always)]
246 pub fn pmd_iter(&self) -> impl Iterator<Item = &PMD> {
247 (0..5).map(move |n| unsafe {
248 &*core::ptr::from_ref(self)
249 .cast::<u8>()
250 .add(4480)
251 .add(60 * n)
252 .cast()
253 })
254 }
255 #[doc = "0x1400..0x17e8 - Cryptographic keys for MPDU encapsulation and decapsulation"]
256 #[inline(always)]
257 pub const fn crypto_key_slot(&self, n: usize) -> &CRYPTO_KEY_SLOT {
258 &self.crypto_key_slot[n]
259 }
260 #[doc = "Iterator for array of:"]
261 #[doc = "0x1400..0x17e8 - Cryptographic keys for MPDU encapsulation and decapsulation"]
262 #[inline(always)]
263 pub fn crypto_key_slot_iter(&self) -> impl Iterator<Item = &CRYPTO_KEY_SLOT> {
264 self.crypto_key_slot.iter()
265 }
266 #[doc = "0x2000 - Current value of the MAC timer"]
267 #[inline(always)]
268 pub const fn mac_time(&self) -> &MAC_TIME {
269 &self.mac_time
270 }
271 #[doc = "0x21a0..0x21a8 - Status and clear for the WIFI_PWR interrupt"]
272 #[inline(always)]
273 pub const fn pwr_interrupt(&self) -> &PWR_INTERRUPT {
274 &self.pwr_interrupt
275 }
276}
277#[doc = "RX_CTRL (rw) register accessor: Controls the reception of frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ctrl`] module"]
278pub type RX_CTRL = crate::Reg<rx_ctrl::RX_CTRL_SPEC>;
279#[doc = "Controls the reception of frames"]
280pub mod rx_ctrl;
281#[doc = "INTERFACE_RX_CONTROL (rw) register accessor: Controls RX for an interface\n\nYou can [`read`](crate::Reg::read) this register and get [`interface_rx_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interface_rx_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interface_rx_control`] module"]
282pub type INTERFACE_RX_CONTROL = crate::Reg<interface_rx_control::INTERFACE_RX_CONTROL_SPEC>;
283#[doc = "Controls RX for an interface"]
284pub mod interface_rx_control;
285#[doc = "CTRL (rw) register accessor: Exact name and meaning unknown, used for initializing the MAC\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
286pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
287#[doc = "Exact name and meaning unknown, used for initializing the MAC"]
288pub mod ctrl;
289#[doc = "PLCP1 (rw) register accessor: PLCP1\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp1`] module"]
290pub type PLCP1 = crate::Reg<plcp1::PLCP1_SPEC>;
291#[doc = "PLCP1"]
292pub mod plcp1;
293#[doc = "PLCP2 (rw) register accessor: PLCP2\n\nYou can [`read`](crate::Reg::read) this register and get [`plcp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plcp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@plcp2`] module"]
294pub type PLCP2 = crate::Reg<plcp2::PLCP2_SPEC>;
295#[doc = "PLCP2"]
296pub mod plcp2;
297#[doc = "HT_SIG (rw) register accessor: HT-SIG field in HT preamble\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_sig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_sig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_sig`] module"]
298pub type HT_SIG = crate::Reg<ht_sig::HT_SIG_SPEC>;
299#[doc = "HT-SIG field in HT preamble"]
300pub mod ht_sig;
301#[doc = "HT_UNKNOWN (rw) register accessor: exact meaning and name unknown, related to HT\n\nYou can [`read`](crate::Reg::read) this register and get [`ht_unknown::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ht_unknown::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ht_unknown`] module"]
302pub type HT_UNKNOWN = crate::Reg<ht_unknown::HT_UNKNOWN_SPEC>;
303#[doc = "exact meaning and name unknown, related to HT"]
304pub mod ht_unknown;
305#[doc = "DURATION (rw) register accessor: duration of the frame exchange\n\nYou can [`read`](crate::Reg::read) this register and get [`duration::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`duration::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@duration`] module"]
306pub type DURATION = crate::Reg<duration::DURATION_SPEC>;
307#[doc = "duration of the frame exchange"]
308pub mod duration;
309#[doc = "PMD (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`pmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmd`] module"]
310pub type PMD = crate::Reg<pmd::PMD_SPEC>;
311#[doc = ""]
312pub mod pmd;
313#[doc = "MAC_TIME (rw) register accessor: Current value of the MAC timer\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_time::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_time::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_time`] module"]
314pub type MAC_TIME = crate::Reg<mac_time::MAC_TIME_SPEC>;
315#[doc = "Current value of the MAC timer"]
316pub mod mac_time;
317#[doc = "Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for four interfaces."]
318pub use self::filter_bank::FILTER_BANK;
319#[doc = r"Cluster"]
320#[doc = "Filter banks for frame reception. Bank zero is for the BSSID and bank one for the RA. Each filter bank has registers for four interfaces."]
321pub mod filter_bank;
322#[doc = "RX_DMA_LIST"]
323pub use self::rx_dma_list::RX_DMA_LIST;
324#[doc = r"Cluster"]
325#[doc = "RX_DMA_LIST"]
326pub mod rx_dma_list;
327#[doc = "Status and clear for the WIFI_MAC interrupt"]
328pub use self::mac_interrupt::MAC_INTERRUPT;
329#[doc = r"Cluster"]
330#[doc = "Status and clear for the WIFI_MAC interrupt"]
331pub mod mac_interrupt;
332#[doc = "Status and clear for the WIFI_PWR interrupt"]
333pub use self::pwr_interrupt::PWR_INTERRUPT;
334#[doc = r"Cluster"]
335#[doc = "Status and clear for the WIFI_PWR interrupt"]
336pub mod pwr_interrupt;
337#[doc = "State of transmission queues"]
338pub use self::txq_state::TXQ_STATE;
339#[doc = r"Cluster"]
340#[doc = "State of transmission queues"]
341pub mod txq_state;
342#[doc = "Used to configure the TX slot."]
343pub use self::tx_slot_config::TX_SLOT_CONFIG;
344#[doc = r"Cluster"]
345#[doc = "Used to configure the TX slot."]
346pub mod tx_slot_config;
347#[doc = "Cryptographic keys for MPDU encapsulation and decapsulation"]
348pub use self::crypto_key_slot::CRYPTO_KEY_SLOT;
349#[doc = r"Cluster"]
350#[doc = "Cryptographic keys for MPDU encapsulation and decapsulation"]
351pub mod crypto_key_slot;
352#[doc = "Control registers for hardware crypto"]
353pub use self::crypto_control::CRYPTO_CONTROL;
354#[doc = r"Cluster"]
355#[doc = "Control registers for hardware crypto"]
356pub mod crypto_control;