esp32s2/pms/
pro_cache_2.rs

1#[doc = "Register `PRO_CACHE_2` reader"]
2pub type R = crate::R<PRO_CACHE_2_SPEC>;
3#[doc = "Register `PRO_CACHE_2` writer"]
4pub type W = crate::W<PRO_CACHE_2_SPEC>;
5#[doc = "Field `PRO_CACHE_ILG_CLR` reader - The clear signal for cache access interrupt."]
6pub type PRO_CACHE_ILG_CLR_R = crate::BitReader;
7#[doc = "Field `PRO_CACHE_ILG_CLR` writer - The clear signal for cache access interrupt."]
8pub type PRO_CACHE_ILG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_CACHE_ILG_EN` reader - The enable signal for cache access interrupt."]
10pub type PRO_CACHE_ILG_EN_R = crate::BitReader;
11#[doc = "Field `PRO_CACHE_ILG_EN` writer - The enable signal for cache access interrupt."]
12pub type PRO_CACHE_ILG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_CACHE_ILG_INTR` reader - Cache access interrupt signal."]
14pub type PRO_CACHE_ILG_INTR_R = crate::BitReader;
15impl R {
16    #[doc = "Bit 0 - The clear signal for cache access interrupt."]
17    #[inline(always)]
18    pub fn pro_cache_ilg_clr(&self) -> PRO_CACHE_ILG_CLR_R {
19        PRO_CACHE_ILG_CLR_R::new((self.bits & 1) != 0)
20    }
21    #[doc = "Bit 1 - The enable signal for cache access interrupt."]
22    #[inline(always)]
23    pub fn pro_cache_ilg_en(&self) -> PRO_CACHE_ILG_EN_R {
24        PRO_CACHE_ILG_EN_R::new(((self.bits >> 1) & 1) != 0)
25    }
26    #[doc = "Bit 2 - Cache access interrupt signal."]
27    #[inline(always)]
28    pub fn pro_cache_ilg_intr(&self) -> PRO_CACHE_ILG_INTR_R {
29        PRO_CACHE_ILG_INTR_R::new(((self.bits >> 2) & 1) != 0)
30    }
31}
32#[cfg(feature = "impl-register-debug")]
33impl core::fmt::Debug for R {
34    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
35        f.debug_struct("PRO_CACHE_2")
36            .field("pro_cache_ilg_clr", &self.pro_cache_ilg_clr())
37            .field("pro_cache_ilg_en", &self.pro_cache_ilg_en())
38            .field("pro_cache_ilg_intr", &self.pro_cache_ilg_intr())
39            .finish()
40    }
41}
42impl W {
43    #[doc = "Bit 0 - The clear signal for cache access interrupt."]
44    #[inline(always)]
45    pub fn pro_cache_ilg_clr(&mut self) -> PRO_CACHE_ILG_CLR_W<PRO_CACHE_2_SPEC> {
46        PRO_CACHE_ILG_CLR_W::new(self, 0)
47    }
48    #[doc = "Bit 1 - The enable signal for cache access interrupt."]
49    #[inline(always)]
50    pub fn pro_cache_ilg_en(&mut self) -> PRO_CACHE_ILG_EN_W<PRO_CACHE_2_SPEC> {
51        PRO_CACHE_ILG_EN_W::new(self, 1)
52    }
53}
54#[doc = "Cache permission control register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_cache_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct PRO_CACHE_2_SPEC;
56impl crate::RegisterSpec for PRO_CACHE_2_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`pro_cache_2::R`](R) reader structure"]
60impl crate::Readable for PRO_CACHE_2_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`pro_cache_2::W`](W) writer structure"]
62impl crate::Writable for PRO_CACHE_2_SPEC {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66}
67#[doc = "`reset()` method sets PRO_CACHE_2 to value 0"]
68impl crate::Resettable for PRO_CACHE_2_SPEC {
69    const RESET_VALUE: u32 = 0;
70}
esp32s2/pms/pro_cache_2.rs

esp32s2/pms/
pro_cache_2.rs
