esp32s2/
extmem.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    pro_dcache_ctrl: PRO_DCACHE_CTRL,
6    pro_dcache_ctrl1: PRO_DCACHE_CTRL1,
7    pro_dcache_tag_power_ctrl: PRO_DCACHE_TAG_POWER_CTRL,
8    pro_dcache_lock0_addr: PRO_DCACHE_LOCK0_ADDR,
9    pro_dcache_lock0_size: PRO_DCACHE_LOCK0_SIZE,
10    pro_dcache_lock1_addr: PRO_DCACHE_LOCK1_ADDR,
11    pro_dcache_lock1_size: PRO_DCACHE_LOCK1_SIZE,
12    pro_dcache_mem_sync0: PRO_DCACHE_MEM_SYNC0,
13    pro_dcache_mem_sync1: PRO_DCACHE_MEM_SYNC1,
14    pro_dcache_preload_addr: PRO_DCACHE_PRELOAD_ADDR,
15    pro_dcache_preload_size: PRO_DCACHE_PRELOAD_SIZE,
16    pro_dcache_autoload_cfg: PRO_DCACHE_AUTOLOAD_CFG,
17    pro_dcache_autoload_section0_addr: PRO_DCACHE_AUTOLOAD_SECTION0_ADDR,
18    pro_dcache_autoload_section0_size: PRO_DCACHE_AUTOLOAD_SECTION0_SIZE,
19    pro_dcache_autoload_section1_addr: PRO_DCACHE_AUTOLOAD_SECTION1_ADDR,
20    pro_dcache_autoload_section1_size: PRO_DCACHE_AUTOLOAD_SECTION1_SIZE,
21    pro_icache_ctrl: PRO_ICACHE_CTRL,
22    pro_icache_ctrl1: PRO_ICACHE_CTRL1,
23    pro_icache_tag_power_ctrl: PRO_ICACHE_TAG_POWER_CTRL,
24    pro_icache_lock0_addr: PRO_ICACHE_LOCK0_ADDR,
25    pro_icache_lock0_size: PRO_ICACHE_LOCK0_SIZE,
26    pro_icache_lock1_addr: PRO_ICACHE_LOCK1_ADDR,
27    pro_icache_lock1_size: PRO_ICACHE_LOCK1_SIZE,
28    pro_icache_mem_sync0: PRO_ICACHE_MEM_SYNC0,
29    pro_icache_mem_sync1: PRO_ICACHE_MEM_SYNC1,
30    pro_icache_preload_addr: PRO_ICACHE_PRELOAD_ADDR,
31    pro_icache_preload_size: PRO_ICACHE_PRELOAD_SIZE,
32    pro_icache_autoload_cfg: PRO_ICACHE_AUTOLOAD_CFG,
33    pro_icache_autoload_section0_addr: PRO_ICACHE_AUTOLOAD_SECTION0_ADDR,
34    pro_icache_autoload_section0_size: PRO_ICACHE_AUTOLOAD_SECTION0_SIZE,
35    pro_icache_autoload_section1_addr: PRO_ICACHE_AUTOLOAD_SECTION1_ADDR,
36    pro_icache_autoload_section1_size: PRO_ICACHE_AUTOLOAD_SECTION1_SIZE,
37    ic_preload_cnt: IC_PRELOAD_CNT,
38    ic_preload_miss_cnt: IC_PRELOAD_MISS_CNT,
39    ibus2_abandon_cnt: IBUS2_ABANDON_CNT,
40    ibus1_abandon_cnt: IBUS1_ABANDON_CNT,
41    ibus0_abandon_cnt: IBUS0_ABANDON_CNT,
42    ibus2_acs_miss_cnt: IBUS2_ACS_MISS_CNT,
43    ibus1_acs_miss_cnt: IBUS1_ACS_MISS_CNT,
44    ibus0_acs_miss_cnt: IBUS0_ACS_MISS_CNT,
45    ibus2_acs_cnt: IBUS2_ACS_CNT,
46    ibus1_acs_cnt: IBUS1_ACS_CNT,
47    ibus0_acs_cnt: IBUS0_ACS_CNT,
48    dc_preload_cnt: DC_PRELOAD_CNT,
49    dc_preload_evict_cnt: DC_PRELOAD_EVICT_CNT,
50    dc_preload_miss_cnt: DC_PRELOAD_MISS_CNT,
51    dbus2_abandon_cnt: DBUS2_ABANDON_CNT,
52    dbus1_abandon_cnt: DBUS1_ABANDON_CNT,
53    dbus0_abandon_cnt: DBUS0_ABANDON_CNT,
54    dbus2_acs_wb_cnt: DBUS2_ACS_WB_CNT,
55    dbus1_acs_wb_cnt: DBUS1_ACS_WB_CNT,
56    dbus0_acs_wb_cnt: DBUS0_ACS_WB_CNT,
57    dbus2_acs_miss_cnt: DBUS2_ACS_MISS_CNT,
58    dbus1_acs_miss_cnt: DBUS1_ACS_MISS_CNT,
59    dbus0_acs_miss_cnt: DBUS0_ACS_MISS_CNT,
60    dbus2_acs_cnt: DBUS2_ACS_CNT,
61    dbus1_acs_cnt: DBUS1_ACS_CNT,
62    dbus0_acs_cnt: DBUS0_ACS_CNT,
63    cache_dbg_int_ena: CACHE_DBG_INT_ENA,
64    cache_dbg_int_clr: CACHE_DBG_INT_CLR,
65    cache_dbg_status0: CACHE_DBG_STATUS0,
66    cache_dbg_status1: CACHE_DBG_STATUS1,
67    pro_cache_acs_cnt_clr: PRO_CACHE_ACS_CNT_CLR,
68    pro_dcache_reject_st: PRO_DCACHE_REJECT_ST,
69    pro_dcache_reject_vaddr: PRO_DCACHE_REJECT_VADDR,
70    pro_icache_reject_st: PRO_ICACHE_REJECT_ST,
71    pro_icache_reject_vaddr: PRO_ICACHE_REJECT_VADDR,
72    pro_cache_mmu_fault_content: PRO_CACHE_MMU_FAULT_CONTENT,
73    pro_cache_mmu_fault_vaddr: PRO_CACHE_MMU_FAULT_VADDR,
74    pro_cache_wrap_around_ctrl: PRO_CACHE_WRAP_AROUND_CTRL,
75    pro_cache_mmu_power_ctrl: PRO_CACHE_MMU_POWER_CTRL,
76    pro_cache_state: PRO_CACHE_STATE,
77    cache_encrypt_decrypt_record_disable: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE,
78    cache_encrypt_decrypt_clk_force_on: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON,
79    cache_bridge_arbiter_ctrl: CACHE_BRIDGE_ARBITER_CTRL,
80    cache_preload_int_ctrl: CACHE_PRELOAD_INT_CTRL,
81    cache_sync_int_ctrl: CACHE_SYNC_INT_CTRL,
82    cache_conf_misc: CACHE_CONF_MISC,
83    clock_gate: CLOCK_GATE,
84    _reserved79: [u8; 0x02c0],
85    pro_extmem_reg_date: PRO_EXTMEM_REG_DATE,
86}
87impl RegisterBlock {
88    #[doc = "0x00 - register description"]
89    #[inline(always)]
90    pub const fn pro_dcache_ctrl(&self) -> &PRO_DCACHE_CTRL {
91        &self.pro_dcache_ctrl
92    }
93    #[doc = "0x04 - register description"]
94    #[inline(always)]
95    pub const fn pro_dcache_ctrl1(&self) -> &PRO_DCACHE_CTRL1 {
96        &self.pro_dcache_ctrl1
97    }
98    #[doc = "0x08 - register description"]
99    #[inline(always)]
100    pub const fn pro_dcache_tag_power_ctrl(&self) -> &PRO_DCACHE_TAG_POWER_CTRL {
101        &self.pro_dcache_tag_power_ctrl
102    }
103    #[doc = "0x0c - register description"]
104    #[inline(always)]
105    pub const fn pro_dcache_lock0_addr(&self) -> &PRO_DCACHE_LOCK0_ADDR {
106        &self.pro_dcache_lock0_addr
107    }
108    #[doc = "0x10 - register description"]
109    #[inline(always)]
110    pub const fn pro_dcache_lock0_size(&self) -> &PRO_DCACHE_LOCK0_SIZE {
111        &self.pro_dcache_lock0_size
112    }
113    #[doc = "0x14 - register description"]
114    #[inline(always)]
115    pub const fn pro_dcache_lock1_addr(&self) -> &PRO_DCACHE_LOCK1_ADDR {
116        &self.pro_dcache_lock1_addr
117    }
118    #[doc = "0x18 - register description"]
119    #[inline(always)]
120    pub const fn pro_dcache_lock1_size(&self) -> &PRO_DCACHE_LOCK1_SIZE {
121        &self.pro_dcache_lock1_size
122    }
123    #[doc = "0x1c - register description"]
124    #[inline(always)]
125    pub const fn pro_dcache_mem_sync0(&self) -> &PRO_DCACHE_MEM_SYNC0 {
126        &self.pro_dcache_mem_sync0
127    }
128    #[doc = "0x20 - register description"]
129    #[inline(always)]
130    pub const fn pro_dcache_mem_sync1(&self) -> &PRO_DCACHE_MEM_SYNC1 {
131        &self.pro_dcache_mem_sync1
132    }
133    #[doc = "0x24 - register description"]
134    #[inline(always)]
135    pub const fn pro_dcache_preload_addr(&self) -> &PRO_DCACHE_PRELOAD_ADDR {
136        &self.pro_dcache_preload_addr
137    }
138    #[doc = "0x28 - register description"]
139    #[inline(always)]
140    pub const fn pro_dcache_preload_size(&self) -> &PRO_DCACHE_PRELOAD_SIZE {
141        &self.pro_dcache_preload_size
142    }
143    #[doc = "0x2c - register description"]
144    #[inline(always)]
145    pub const fn pro_dcache_autoload_cfg(&self) -> &PRO_DCACHE_AUTOLOAD_CFG {
146        &self.pro_dcache_autoload_cfg
147    }
148    #[doc = "0x30 - register description"]
149    #[inline(always)]
150    pub const fn pro_dcache_autoload_section0_addr(&self) -> &PRO_DCACHE_AUTOLOAD_SECTION0_ADDR {
151        &self.pro_dcache_autoload_section0_addr
152    }
153    #[doc = "0x34 - register description"]
154    #[inline(always)]
155    pub const fn pro_dcache_autoload_section0_size(&self) -> &PRO_DCACHE_AUTOLOAD_SECTION0_SIZE {
156        &self.pro_dcache_autoload_section0_size
157    }
158    #[doc = "0x38 - register description"]
159    #[inline(always)]
160    pub const fn pro_dcache_autoload_section1_addr(&self) -> &PRO_DCACHE_AUTOLOAD_SECTION1_ADDR {
161        &self.pro_dcache_autoload_section1_addr
162    }
163    #[doc = "0x3c - register description"]
164    #[inline(always)]
165    pub const fn pro_dcache_autoload_section1_size(&self) -> &PRO_DCACHE_AUTOLOAD_SECTION1_SIZE {
166        &self.pro_dcache_autoload_section1_size
167    }
168    #[doc = "0x40 - register description"]
169    #[inline(always)]
170    pub const fn pro_icache_ctrl(&self) -> &PRO_ICACHE_CTRL {
171        &self.pro_icache_ctrl
172    }
173    #[doc = "0x44 - register description"]
174    #[inline(always)]
175    pub const fn pro_icache_ctrl1(&self) -> &PRO_ICACHE_CTRL1 {
176        &self.pro_icache_ctrl1
177    }
178    #[doc = "0x48 - register description"]
179    #[inline(always)]
180    pub const fn pro_icache_tag_power_ctrl(&self) -> &PRO_ICACHE_TAG_POWER_CTRL {
181        &self.pro_icache_tag_power_ctrl
182    }
183    #[doc = "0x4c - register description"]
184    #[inline(always)]
185    pub const fn pro_icache_lock0_addr(&self) -> &PRO_ICACHE_LOCK0_ADDR {
186        &self.pro_icache_lock0_addr
187    }
188    #[doc = "0x50 - register description"]
189    #[inline(always)]
190    pub const fn pro_icache_lock0_size(&self) -> &PRO_ICACHE_LOCK0_SIZE {
191        &self.pro_icache_lock0_size
192    }
193    #[doc = "0x54 - register description"]
194    #[inline(always)]
195    pub const fn pro_icache_lock1_addr(&self) -> &PRO_ICACHE_LOCK1_ADDR {
196        &self.pro_icache_lock1_addr
197    }
198    #[doc = "0x58 - register description"]
199    #[inline(always)]
200    pub const fn pro_icache_lock1_size(&self) -> &PRO_ICACHE_LOCK1_SIZE {
201        &self.pro_icache_lock1_size
202    }
203    #[doc = "0x5c - register description"]
204    #[inline(always)]
205    pub const fn pro_icache_mem_sync0(&self) -> &PRO_ICACHE_MEM_SYNC0 {
206        &self.pro_icache_mem_sync0
207    }
208    #[doc = "0x60 - register description"]
209    #[inline(always)]
210    pub const fn pro_icache_mem_sync1(&self) -> &PRO_ICACHE_MEM_SYNC1 {
211        &self.pro_icache_mem_sync1
212    }
213    #[doc = "0x64 - register description"]
214    #[inline(always)]
215    pub const fn pro_icache_preload_addr(&self) -> &PRO_ICACHE_PRELOAD_ADDR {
216        &self.pro_icache_preload_addr
217    }
218    #[doc = "0x68 - register description"]
219    #[inline(always)]
220    pub const fn pro_icache_preload_size(&self) -> &PRO_ICACHE_PRELOAD_SIZE {
221        &self.pro_icache_preload_size
222    }
223    #[doc = "0x6c - register description"]
224    #[inline(always)]
225    pub const fn pro_icache_autoload_cfg(&self) -> &PRO_ICACHE_AUTOLOAD_CFG {
226        &self.pro_icache_autoload_cfg
227    }
228    #[doc = "0x70 - register description"]
229    #[inline(always)]
230    pub const fn pro_icache_autoload_section0_addr(&self) -> &PRO_ICACHE_AUTOLOAD_SECTION0_ADDR {
231        &self.pro_icache_autoload_section0_addr
232    }
233    #[doc = "0x74 - register description"]
234    #[inline(always)]
235    pub const fn pro_icache_autoload_section0_size(&self) -> &PRO_ICACHE_AUTOLOAD_SECTION0_SIZE {
236        &self.pro_icache_autoload_section0_size
237    }
238    #[doc = "0x78 - register description"]
239    #[inline(always)]
240    pub const fn pro_icache_autoload_section1_addr(&self) -> &PRO_ICACHE_AUTOLOAD_SECTION1_ADDR {
241        &self.pro_icache_autoload_section1_addr
242    }
243    #[doc = "0x7c - register description"]
244    #[inline(always)]
245    pub const fn pro_icache_autoload_section1_size(&self) -> &PRO_ICACHE_AUTOLOAD_SECTION1_SIZE {
246        &self.pro_icache_autoload_section1_size
247    }
248    #[doc = "0x80 - register description"]
249    #[inline(always)]
250    pub const fn ic_preload_cnt(&self) -> &IC_PRELOAD_CNT {
251        &self.ic_preload_cnt
252    }
253    #[doc = "0x84 - register description"]
254    #[inline(always)]
255    pub const fn ic_preload_miss_cnt(&self) -> &IC_PRELOAD_MISS_CNT {
256        &self.ic_preload_miss_cnt
257    }
258    #[doc = "0x88 - register description"]
259    #[inline(always)]
260    pub const fn ibus2_abandon_cnt(&self) -> &IBUS2_ABANDON_CNT {
261        &self.ibus2_abandon_cnt
262    }
263    #[doc = "0x8c - register description"]
264    #[inline(always)]
265    pub const fn ibus1_abandon_cnt(&self) -> &IBUS1_ABANDON_CNT {
266        &self.ibus1_abandon_cnt
267    }
268    #[doc = "0x90 - register description"]
269    #[inline(always)]
270    pub const fn ibus0_abandon_cnt(&self) -> &IBUS0_ABANDON_CNT {
271        &self.ibus0_abandon_cnt
272    }
273    #[doc = "0x94 - register description"]
274    #[inline(always)]
275    pub const fn ibus2_acs_miss_cnt(&self) -> &IBUS2_ACS_MISS_CNT {
276        &self.ibus2_acs_miss_cnt
277    }
278    #[doc = "0x98 - register description"]
279    #[inline(always)]
280    pub const fn ibus1_acs_miss_cnt(&self) -> &IBUS1_ACS_MISS_CNT {
281        &self.ibus1_acs_miss_cnt
282    }
283    #[doc = "0x9c - register description"]
284    #[inline(always)]
285    pub const fn ibus0_acs_miss_cnt(&self) -> &IBUS0_ACS_MISS_CNT {
286        &self.ibus0_acs_miss_cnt
287    }
288    #[doc = "0xa0 - register description"]
289    #[inline(always)]
290    pub const fn ibus2_acs_cnt(&self) -> &IBUS2_ACS_CNT {
291        &self.ibus2_acs_cnt
292    }
293    #[doc = "0xa4 - register description"]
294    #[inline(always)]
295    pub const fn ibus1_acs_cnt(&self) -> &IBUS1_ACS_CNT {
296        &self.ibus1_acs_cnt
297    }
298    #[doc = "0xa8 - register description"]
299    #[inline(always)]
300    pub const fn ibus0_acs_cnt(&self) -> &IBUS0_ACS_CNT {
301        &self.ibus0_acs_cnt
302    }
303    #[doc = "0xac - register description"]
304    #[inline(always)]
305    pub const fn dc_preload_cnt(&self) -> &DC_PRELOAD_CNT {
306        &self.dc_preload_cnt
307    }
308    #[doc = "0xb0 - register description"]
309    #[inline(always)]
310    pub const fn dc_preload_evict_cnt(&self) -> &DC_PRELOAD_EVICT_CNT {
311        &self.dc_preload_evict_cnt
312    }
313    #[doc = "0xb4 - register description"]
314    #[inline(always)]
315    pub const fn dc_preload_miss_cnt(&self) -> &DC_PRELOAD_MISS_CNT {
316        &self.dc_preload_miss_cnt
317    }
318    #[doc = "0xb8 - register description"]
319    #[inline(always)]
320    pub const fn dbus2_abandon_cnt(&self) -> &DBUS2_ABANDON_CNT {
321        &self.dbus2_abandon_cnt
322    }
323    #[doc = "0xbc - register description"]
324    #[inline(always)]
325    pub const fn dbus1_abandon_cnt(&self) -> &DBUS1_ABANDON_CNT {
326        &self.dbus1_abandon_cnt
327    }
328    #[doc = "0xc0 - register description"]
329    #[inline(always)]
330    pub const fn dbus0_abandon_cnt(&self) -> &DBUS0_ABANDON_CNT {
331        &self.dbus0_abandon_cnt
332    }
333    #[doc = "0xc4 - register description"]
334    #[inline(always)]
335    pub const fn dbus2_acs_wb_cnt(&self) -> &DBUS2_ACS_WB_CNT {
336        &self.dbus2_acs_wb_cnt
337    }
338    #[doc = "0xc8 - register description"]
339    #[inline(always)]
340    pub const fn dbus1_acs_wb_cnt(&self) -> &DBUS1_ACS_WB_CNT {
341        &self.dbus1_acs_wb_cnt
342    }
343    #[doc = "0xcc - register description"]
344    #[inline(always)]
345    pub const fn dbus0_acs_wb_cnt(&self) -> &DBUS0_ACS_WB_CNT {
346        &self.dbus0_acs_wb_cnt
347    }
348    #[doc = "0xd0 - register description"]
349    #[inline(always)]
350    pub const fn dbus2_acs_miss_cnt(&self) -> &DBUS2_ACS_MISS_CNT {
351        &self.dbus2_acs_miss_cnt
352    }
353    #[doc = "0xd4 - register description"]
354    #[inline(always)]
355    pub const fn dbus1_acs_miss_cnt(&self) -> &DBUS1_ACS_MISS_CNT {
356        &self.dbus1_acs_miss_cnt
357    }
358    #[doc = "0xd8 - register description"]
359    #[inline(always)]
360    pub const fn dbus0_acs_miss_cnt(&self) -> &DBUS0_ACS_MISS_CNT {
361        &self.dbus0_acs_miss_cnt
362    }
363    #[doc = "0xdc - register description"]
364    #[inline(always)]
365    pub const fn dbus2_acs_cnt(&self) -> &DBUS2_ACS_CNT {
366        &self.dbus2_acs_cnt
367    }
368    #[doc = "0xe0 - register description"]
369    #[inline(always)]
370    pub const fn dbus1_acs_cnt(&self) -> &DBUS1_ACS_CNT {
371        &self.dbus1_acs_cnt
372    }
373    #[doc = "0xe4 - register description"]
374    #[inline(always)]
375    pub const fn dbus0_acs_cnt(&self) -> &DBUS0_ACS_CNT {
376        &self.dbus0_acs_cnt
377    }
378    #[doc = "0xe8 - register description"]
379    #[inline(always)]
380    pub const fn cache_dbg_int_ena(&self) -> &CACHE_DBG_INT_ENA {
381        &self.cache_dbg_int_ena
382    }
383    #[doc = "0xec - register description"]
384    #[inline(always)]
385    pub const fn cache_dbg_int_clr(&self) -> &CACHE_DBG_INT_CLR {
386        &self.cache_dbg_int_clr
387    }
388    #[doc = "0xf0 - register description"]
389    #[inline(always)]
390    pub const fn cache_dbg_status0(&self) -> &CACHE_DBG_STATUS0 {
391        &self.cache_dbg_status0
392    }
393    #[doc = "0xf4 - register description"]
394    #[inline(always)]
395    pub const fn cache_dbg_status1(&self) -> &CACHE_DBG_STATUS1 {
396        &self.cache_dbg_status1
397    }
398    #[doc = "0xf8 - register description"]
399    #[inline(always)]
400    pub const fn pro_cache_acs_cnt_clr(&self) -> &PRO_CACHE_ACS_CNT_CLR {
401        &self.pro_cache_acs_cnt_clr
402    }
403    #[doc = "0xfc - register description"]
404    #[inline(always)]
405    pub const fn pro_dcache_reject_st(&self) -> &PRO_DCACHE_REJECT_ST {
406        &self.pro_dcache_reject_st
407    }
408    #[doc = "0x100 - register description"]
409    #[inline(always)]
410    pub const fn pro_dcache_reject_vaddr(&self) -> &PRO_DCACHE_REJECT_VADDR {
411        &self.pro_dcache_reject_vaddr
412    }
413    #[doc = "0x104 - register description"]
414    #[inline(always)]
415    pub const fn pro_icache_reject_st(&self) -> &PRO_ICACHE_REJECT_ST {
416        &self.pro_icache_reject_st
417    }
418    #[doc = "0x108 - register description"]
419    #[inline(always)]
420    pub const fn pro_icache_reject_vaddr(&self) -> &PRO_ICACHE_REJECT_VADDR {
421        &self.pro_icache_reject_vaddr
422    }
423    #[doc = "0x10c - register description"]
424    #[inline(always)]
425    pub const fn pro_cache_mmu_fault_content(&self) -> &PRO_CACHE_MMU_FAULT_CONTENT {
426        &self.pro_cache_mmu_fault_content
427    }
428    #[doc = "0x110 - register description"]
429    #[inline(always)]
430    pub const fn pro_cache_mmu_fault_vaddr(&self) -> &PRO_CACHE_MMU_FAULT_VADDR {
431        &self.pro_cache_mmu_fault_vaddr
432    }
433    #[doc = "0x114 - register description"]
434    #[inline(always)]
435    pub const fn pro_cache_wrap_around_ctrl(&self) -> &PRO_CACHE_WRAP_AROUND_CTRL {
436        &self.pro_cache_wrap_around_ctrl
437    }
438    #[doc = "0x118 - register description"]
439    #[inline(always)]
440    pub const fn pro_cache_mmu_power_ctrl(&self) -> &PRO_CACHE_MMU_POWER_CTRL {
441        &self.pro_cache_mmu_power_ctrl
442    }
443    #[doc = "0x11c - register description"]
444    #[inline(always)]
445    pub const fn pro_cache_state(&self) -> &PRO_CACHE_STATE {
446        &self.pro_cache_state
447    }
448    #[doc = "0x120 - register description"]
449    #[inline(always)]
450    pub const fn cache_encrypt_decrypt_record_disable(
451        &self,
452    ) -> &CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE {
453        &self.cache_encrypt_decrypt_record_disable
454    }
455    #[doc = "0x124 - register description"]
456    #[inline(always)]
457    pub const fn cache_encrypt_decrypt_clk_force_on(&self) -> &CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON {
458        &self.cache_encrypt_decrypt_clk_force_on
459    }
460    #[doc = "0x128 - register description"]
461    #[inline(always)]
462    pub const fn cache_bridge_arbiter_ctrl(&self) -> &CACHE_BRIDGE_ARBITER_CTRL {
463        &self.cache_bridge_arbiter_ctrl
464    }
465    #[doc = "0x12c - register description"]
466    #[inline(always)]
467    pub const fn cache_preload_int_ctrl(&self) -> &CACHE_PRELOAD_INT_CTRL {
468        &self.cache_preload_int_ctrl
469    }
470    #[doc = "0x130 - register description"]
471    #[inline(always)]
472    pub const fn cache_sync_int_ctrl(&self) -> &CACHE_SYNC_INT_CTRL {
473        &self.cache_sync_int_ctrl
474    }
475    #[doc = "0x134 - register description"]
476    #[inline(always)]
477    pub const fn cache_conf_misc(&self) -> &CACHE_CONF_MISC {
478        &self.cache_conf_misc
479    }
480    #[doc = "0x138 - register description"]
481    #[inline(always)]
482    pub const fn clock_gate(&self) -> &CLOCK_GATE {
483        &self.clock_gate
484    }
485    #[doc = "0x3fc - register description"]
486    #[inline(always)]
487    pub const fn pro_extmem_reg_date(&self) -> &PRO_EXTMEM_REG_DATE {
488        &self.pro_extmem_reg_date
489    }
490}
491#[doc = "PRO_DCACHE_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_ctrl`] module"]
492pub type PRO_DCACHE_CTRL = crate::Reg<pro_dcache_ctrl::PRO_DCACHE_CTRL_SPEC>;
493#[doc = "register description"]
494pub mod pro_dcache_ctrl;
495#[doc = "PRO_DCACHE_CTRL1 (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_ctrl1`] module"]
496pub type PRO_DCACHE_CTRL1 = crate::Reg<pro_dcache_ctrl1::PRO_DCACHE_CTRL1_SPEC>;
497#[doc = "register description"]
498pub mod pro_dcache_ctrl1;
499#[doc = "PRO_DCACHE_TAG_POWER_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_tag_power_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_tag_power_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_tag_power_ctrl`] module"]
500pub type PRO_DCACHE_TAG_POWER_CTRL =
501    crate::Reg<pro_dcache_tag_power_ctrl::PRO_DCACHE_TAG_POWER_CTRL_SPEC>;
502#[doc = "register description"]
503pub mod pro_dcache_tag_power_ctrl;
504#[doc = "PRO_DCACHE_LOCK0_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_lock0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_lock0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_lock0_addr`] module"]
505pub type PRO_DCACHE_LOCK0_ADDR = crate::Reg<pro_dcache_lock0_addr::PRO_DCACHE_LOCK0_ADDR_SPEC>;
506#[doc = "register description"]
507pub mod pro_dcache_lock0_addr;
508#[doc = "PRO_DCACHE_LOCK0_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_lock0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_lock0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_lock0_size`] module"]
509pub type PRO_DCACHE_LOCK0_SIZE = crate::Reg<pro_dcache_lock0_size::PRO_DCACHE_LOCK0_SIZE_SPEC>;
510#[doc = "register description"]
511pub mod pro_dcache_lock0_size;
512#[doc = "PRO_DCACHE_LOCK1_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_lock1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_lock1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_lock1_addr`] module"]
513pub type PRO_DCACHE_LOCK1_ADDR = crate::Reg<pro_dcache_lock1_addr::PRO_DCACHE_LOCK1_ADDR_SPEC>;
514#[doc = "register description"]
515pub mod pro_dcache_lock1_addr;
516#[doc = "PRO_DCACHE_LOCK1_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_lock1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_lock1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_lock1_size`] module"]
517pub type PRO_DCACHE_LOCK1_SIZE = crate::Reg<pro_dcache_lock1_size::PRO_DCACHE_LOCK1_SIZE_SPEC>;
518#[doc = "register description"]
519pub mod pro_dcache_lock1_size;
520#[doc = "PRO_DCACHE_MEM_SYNC0 (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_mem_sync0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_mem_sync0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_mem_sync0`] module"]
521pub type PRO_DCACHE_MEM_SYNC0 = crate::Reg<pro_dcache_mem_sync0::PRO_DCACHE_MEM_SYNC0_SPEC>;
522#[doc = "register description"]
523pub mod pro_dcache_mem_sync0;
524#[doc = "PRO_DCACHE_MEM_SYNC1 (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_mem_sync1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_mem_sync1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_mem_sync1`] module"]
525pub type PRO_DCACHE_MEM_SYNC1 = crate::Reg<pro_dcache_mem_sync1::PRO_DCACHE_MEM_SYNC1_SPEC>;
526#[doc = "register description"]
527pub mod pro_dcache_mem_sync1;
528#[doc = "PRO_DCACHE_PRELOAD_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_preload_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_preload_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_preload_addr`] module"]
529pub type PRO_DCACHE_PRELOAD_ADDR =
530    crate::Reg<pro_dcache_preload_addr::PRO_DCACHE_PRELOAD_ADDR_SPEC>;
531#[doc = "register description"]
532pub mod pro_dcache_preload_addr;
533#[doc = "PRO_DCACHE_PRELOAD_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_preload_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_preload_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_preload_size`] module"]
534pub type PRO_DCACHE_PRELOAD_SIZE =
535    crate::Reg<pro_dcache_preload_size::PRO_DCACHE_PRELOAD_SIZE_SPEC>;
536#[doc = "register description"]
537pub mod pro_dcache_preload_size;
538#[doc = "PRO_DCACHE_AUTOLOAD_CFG (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_autoload_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_autoload_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_autoload_cfg`] module"]
539pub type PRO_DCACHE_AUTOLOAD_CFG =
540    crate::Reg<pro_dcache_autoload_cfg::PRO_DCACHE_AUTOLOAD_CFG_SPEC>;
541#[doc = "register description"]
542pub mod pro_dcache_autoload_cfg;
543#[doc = "PRO_DCACHE_AUTOLOAD_SECTION0_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_autoload_section0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_autoload_section0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_autoload_section0_addr`] module"]
544pub type PRO_DCACHE_AUTOLOAD_SECTION0_ADDR =
545    crate::Reg<pro_dcache_autoload_section0_addr::PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_SPEC>;
546#[doc = "register description"]
547pub mod pro_dcache_autoload_section0_addr;
548#[doc = "PRO_DCACHE_AUTOLOAD_SECTION0_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_autoload_section0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_autoload_section0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_autoload_section0_size`] module"]
549pub type PRO_DCACHE_AUTOLOAD_SECTION0_SIZE =
550    crate::Reg<pro_dcache_autoload_section0_size::PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_SPEC>;
551#[doc = "register description"]
552pub mod pro_dcache_autoload_section0_size;
553#[doc = "PRO_DCACHE_AUTOLOAD_SECTION1_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_autoload_section1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_autoload_section1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_autoload_section1_addr`] module"]
554pub type PRO_DCACHE_AUTOLOAD_SECTION1_ADDR =
555    crate::Reg<pro_dcache_autoload_section1_addr::PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_SPEC>;
556#[doc = "register description"]
557pub mod pro_dcache_autoload_section1_addr;
558#[doc = "PRO_DCACHE_AUTOLOAD_SECTION1_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_autoload_section1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_autoload_section1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_autoload_section1_size`] module"]
559pub type PRO_DCACHE_AUTOLOAD_SECTION1_SIZE =
560    crate::Reg<pro_dcache_autoload_section1_size::PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_SPEC>;
561#[doc = "register description"]
562pub mod pro_dcache_autoload_section1_size;
563#[doc = "PRO_ICACHE_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_ctrl`] module"]
564pub type PRO_ICACHE_CTRL = crate::Reg<pro_icache_ctrl::PRO_ICACHE_CTRL_SPEC>;
565#[doc = "register description"]
566pub mod pro_icache_ctrl;
567#[doc = "PRO_ICACHE_CTRL1 (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_ctrl1`] module"]
568pub type PRO_ICACHE_CTRL1 = crate::Reg<pro_icache_ctrl1::PRO_ICACHE_CTRL1_SPEC>;
569#[doc = "register description"]
570pub mod pro_icache_ctrl1;
571#[doc = "PRO_ICACHE_TAG_POWER_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_tag_power_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_tag_power_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_tag_power_ctrl`] module"]
572pub type PRO_ICACHE_TAG_POWER_CTRL =
573    crate::Reg<pro_icache_tag_power_ctrl::PRO_ICACHE_TAG_POWER_CTRL_SPEC>;
574#[doc = "register description"]
575pub mod pro_icache_tag_power_ctrl;
576#[doc = "PRO_ICACHE_LOCK0_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_lock0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_lock0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_lock0_addr`] module"]
577pub type PRO_ICACHE_LOCK0_ADDR = crate::Reg<pro_icache_lock0_addr::PRO_ICACHE_LOCK0_ADDR_SPEC>;
578#[doc = "register description"]
579pub mod pro_icache_lock0_addr;
580#[doc = "PRO_ICACHE_LOCK0_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_lock0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_lock0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_lock0_size`] module"]
581pub type PRO_ICACHE_LOCK0_SIZE = crate::Reg<pro_icache_lock0_size::PRO_ICACHE_LOCK0_SIZE_SPEC>;
582#[doc = "register description"]
583pub mod pro_icache_lock0_size;
584#[doc = "PRO_ICACHE_LOCK1_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_lock1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_lock1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_lock1_addr`] module"]
585pub type PRO_ICACHE_LOCK1_ADDR = crate::Reg<pro_icache_lock1_addr::PRO_ICACHE_LOCK1_ADDR_SPEC>;
586#[doc = "register description"]
587pub mod pro_icache_lock1_addr;
588#[doc = "PRO_ICACHE_LOCK1_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_lock1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_lock1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_lock1_size`] module"]
589pub type PRO_ICACHE_LOCK1_SIZE = crate::Reg<pro_icache_lock1_size::PRO_ICACHE_LOCK1_SIZE_SPEC>;
590#[doc = "register description"]
591pub mod pro_icache_lock1_size;
592#[doc = "PRO_ICACHE_MEM_SYNC0 (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_mem_sync0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_mem_sync0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_mem_sync0`] module"]
593pub type PRO_ICACHE_MEM_SYNC0 = crate::Reg<pro_icache_mem_sync0::PRO_ICACHE_MEM_SYNC0_SPEC>;
594#[doc = "register description"]
595pub mod pro_icache_mem_sync0;
596#[doc = "PRO_ICACHE_MEM_SYNC1 (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_mem_sync1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_mem_sync1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_mem_sync1`] module"]
597pub type PRO_ICACHE_MEM_SYNC1 = crate::Reg<pro_icache_mem_sync1::PRO_ICACHE_MEM_SYNC1_SPEC>;
598#[doc = "register description"]
599pub mod pro_icache_mem_sync1;
600#[doc = "PRO_ICACHE_PRELOAD_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_preload_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_preload_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_preload_addr`] module"]
601pub type PRO_ICACHE_PRELOAD_ADDR =
602    crate::Reg<pro_icache_preload_addr::PRO_ICACHE_PRELOAD_ADDR_SPEC>;
603#[doc = "register description"]
604pub mod pro_icache_preload_addr;
605#[doc = "PRO_ICACHE_PRELOAD_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_preload_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_preload_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_preload_size`] module"]
606pub type PRO_ICACHE_PRELOAD_SIZE =
607    crate::Reg<pro_icache_preload_size::PRO_ICACHE_PRELOAD_SIZE_SPEC>;
608#[doc = "register description"]
609pub mod pro_icache_preload_size;
610#[doc = "PRO_ICACHE_AUTOLOAD_CFG (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_autoload_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_autoload_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_autoload_cfg`] module"]
611pub type PRO_ICACHE_AUTOLOAD_CFG =
612    crate::Reg<pro_icache_autoload_cfg::PRO_ICACHE_AUTOLOAD_CFG_SPEC>;
613#[doc = "register description"]
614pub mod pro_icache_autoload_cfg;
615#[doc = "PRO_ICACHE_AUTOLOAD_SECTION0_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_autoload_section0_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_autoload_section0_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_autoload_section0_addr`] module"]
616pub type PRO_ICACHE_AUTOLOAD_SECTION0_ADDR =
617    crate::Reg<pro_icache_autoload_section0_addr::PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_SPEC>;
618#[doc = "register description"]
619pub mod pro_icache_autoload_section0_addr;
620#[doc = "PRO_ICACHE_AUTOLOAD_SECTION0_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_autoload_section0_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_autoload_section0_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_autoload_section0_size`] module"]
621pub type PRO_ICACHE_AUTOLOAD_SECTION0_SIZE =
622    crate::Reg<pro_icache_autoload_section0_size::PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_SPEC>;
623#[doc = "register description"]
624pub mod pro_icache_autoload_section0_size;
625#[doc = "PRO_ICACHE_AUTOLOAD_SECTION1_ADDR (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_autoload_section1_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_autoload_section1_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_autoload_section1_addr`] module"]
626pub type PRO_ICACHE_AUTOLOAD_SECTION1_ADDR =
627    crate::Reg<pro_icache_autoload_section1_addr::PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_SPEC>;
628#[doc = "register description"]
629pub mod pro_icache_autoload_section1_addr;
630#[doc = "PRO_ICACHE_AUTOLOAD_SECTION1_SIZE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_autoload_section1_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_autoload_section1_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_autoload_section1_size`] module"]
631pub type PRO_ICACHE_AUTOLOAD_SECTION1_SIZE =
632    crate::Reg<pro_icache_autoload_section1_size::PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_SPEC>;
633#[doc = "register description"]
634pub mod pro_icache_autoload_section1_size;
635#[doc = "IC_PRELOAD_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_preload_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_preload_cnt`] module"]
636pub type IC_PRELOAD_CNT = crate::Reg<ic_preload_cnt::IC_PRELOAD_CNT_SPEC>;
637#[doc = "register description"]
638pub mod ic_preload_cnt;
639#[doc = "IC_PRELOAD_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ic_preload_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic_preload_miss_cnt`] module"]
640pub type IC_PRELOAD_MISS_CNT = crate::Reg<ic_preload_miss_cnt::IC_PRELOAD_MISS_CNT_SPEC>;
641#[doc = "register description"]
642pub mod ic_preload_miss_cnt;
643#[doc = "IBUS2_ABANDON_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus2_abandon_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus2_abandon_cnt`] module"]
644pub type IBUS2_ABANDON_CNT = crate::Reg<ibus2_abandon_cnt::IBUS2_ABANDON_CNT_SPEC>;
645#[doc = "register description"]
646pub mod ibus2_abandon_cnt;
647#[doc = "IBUS1_ABANDON_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus1_abandon_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus1_abandon_cnt`] module"]
648pub type IBUS1_ABANDON_CNT = crate::Reg<ibus1_abandon_cnt::IBUS1_ABANDON_CNT_SPEC>;
649#[doc = "register description"]
650pub mod ibus1_abandon_cnt;
651#[doc = "IBUS0_ABANDON_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus0_abandon_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus0_abandon_cnt`] module"]
652pub type IBUS0_ABANDON_CNT = crate::Reg<ibus0_abandon_cnt::IBUS0_ABANDON_CNT_SPEC>;
653#[doc = "register description"]
654pub mod ibus0_abandon_cnt;
655#[doc = "IBUS2_ACS_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus2_acs_miss_cnt`] module"]
656pub type IBUS2_ACS_MISS_CNT = crate::Reg<ibus2_acs_miss_cnt::IBUS2_ACS_MISS_CNT_SPEC>;
657#[doc = "register description"]
658pub mod ibus2_acs_miss_cnt;
659#[doc = "IBUS1_ACS_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus1_acs_miss_cnt`] module"]
660pub type IBUS1_ACS_MISS_CNT = crate::Reg<ibus1_acs_miss_cnt::IBUS1_ACS_MISS_CNT_SPEC>;
661#[doc = "register description"]
662pub mod ibus1_acs_miss_cnt;
663#[doc = "IBUS0_ACS_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus0_acs_miss_cnt`] module"]
664pub type IBUS0_ACS_MISS_CNT = crate::Reg<ibus0_acs_miss_cnt::IBUS0_ACS_MISS_CNT_SPEC>;
665#[doc = "register description"]
666pub mod ibus0_acs_miss_cnt;
667#[doc = "IBUS2_ACS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus2_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus2_acs_cnt`] module"]
668pub type IBUS2_ACS_CNT = crate::Reg<ibus2_acs_cnt::IBUS2_ACS_CNT_SPEC>;
669#[doc = "register description"]
670pub mod ibus2_acs_cnt;
671#[doc = "IBUS1_ACS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus1_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus1_acs_cnt`] module"]
672pub type IBUS1_ACS_CNT = crate::Reg<ibus1_acs_cnt::IBUS1_ACS_CNT_SPEC>;
673#[doc = "register description"]
674pub mod ibus1_acs_cnt;
675#[doc = "IBUS0_ACS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`ibus0_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibus0_acs_cnt`] module"]
676pub type IBUS0_ACS_CNT = crate::Reg<ibus0_acs_cnt::IBUS0_ACS_CNT_SPEC>;
677#[doc = "register description"]
678pub mod ibus0_acs_cnt;
679#[doc = "DC_PRELOAD_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_preload_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_preload_cnt`] module"]
680pub type DC_PRELOAD_CNT = crate::Reg<dc_preload_cnt::DC_PRELOAD_CNT_SPEC>;
681#[doc = "register description"]
682pub mod dc_preload_cnt;
683#[doc = "DC_PRELOAD_EVICT_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_preload_evict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_preload_evict_cnt`] module"]
684pub type DC_PRELOAD_EVICT_CNT = crate::Reg<dc_preload_evict_cnt::DC_PRELOAD_EVICT_CNT_SPEC>;
685#[doc = "register description"]
686pub mod dc_preload_evict_cnt;
687#[doc = "DC_PRELOAD_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dc_preload_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc_preload_miss_cnt`] module"]
688pub type DC_PRELOAD_MISS_CNT = crate::Reg<dc_preload_miss_cnt::DC_PRELOAD_MISS_CNT_SPEC>;
689#[doc = "register description"]
690pub mod dc_preload_miss_cnt;
691#[doc = "DBUS2_ABANDON_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus2_abandon_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus2_abandon_cnt`] module"]
692pub type DBUS2_ABANDON_CNT = crate::Reg<dbus2_abandon_cnt::DBUS2_ABANDON_CNT_SPEC>;
693#[doc = "register description"]
694pub mod dbus2_abandon_cnt;
695#[doc = "DBUS1_ABANDON_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus1_abandon_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus1_abandon_cnt`] module"]
696pub type DBUS1_ABANDON_CNT = crate::Reg<dbus1_abandon_cnt::DBUS1_ABANDON_CNT_SPEC>;
697#[doc = "register description"]
698pub mod dbus1_abandon_cnt;
699#[doc = "DBUS0_ABANDON_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus0_abandon_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus0_abandon_cnt`] module"]
700pub type DBUS0_ABANDON_CNT = crate::Reg<dbus0_abandon_cnt::DBUS0_ABANDON_CNT_SPEC>;
701#[doc = "register description"]
702pub mod dbus0_abandon_cnt;
703#[doc = "DBUS2_ACS_WB_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus2_acs_wb_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus2_acs_wb_cnt`] module"]
704pub type DBUS2_ACS_WB_CNT = crate::Reg<dbus2_acs_wb_cnt::DBUS2_ACS_WB_CNT_SPEC>;
705#[doc = "register description"]
706pub mod dbus2_acs_wb_cnt;
707#[doc = "DBUS1_ACS_WB_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus1_acs_wb_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus1_acs_wb_cnt`] module"]
708pub type DBUS1_ACS_WB_CNT = crate::Reg<dbus1_acs_wb_cnt::DBUS1_ACS_WB_CNT_SPEC>;
709#[doc = "register description"]
710pub mod dbus1_acs_wb_cnt;
711#[doc = "DBUS0_ACS_WB_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus0_acs_wb_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus0_acs_wb_cnt`] module"]
712pub type DBUS0_ACS_WB_CNT = crate::Reg<dbus0_acs_wb_cnt::DBUS0_ACS_WB_CNT_SPEC>;
713#[doc = "register description"]
714pub mod dbus0_acs_wb_cnt;
715#[doc = "DBUS2_ACS_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus2_acs_miss_cnt`] module"]
716pub type DBUS2_ACS_MISS_CNT = crate::Reg<dbus2_acs_miss_cnt::DBUS2_ACS_MISS_CNT_SPEC>;
717#[doc = "register description"]
718pub mod dbus2_acs_miss_cnt;
719#[doc = "DBUS1_ACS_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus1_acs_miss_cnt`] module"]
720pub type DBUS1_ACS_MISS_CNT = crate::Reg<dbus1_acs_miss_cnt::DBUS1_ACS_MISS_CNT_SPEC>;
721#[doc = "register description"]
722pub mod dbus1_acs_miss_cnt;
723#[doc = "DBUS0_ACS_MISS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus0_acs_miss_cnt`] module"]
724pub type DBUS0_ACS_MISS_CNT = crate::Reg<dbus0_acs_miss_cnt::DBUS0_ACS_MISS_CNT_SPEC>;
725#[doc = "register description"]
726pub mod dbus0_acs_miss_cnt;
727#[doc = "DBUS2_ACS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus2_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus2_acs_cnt`] module"]
728pub type DBUS2_ACS_CNT = crate::Reg<dbus2_acs_cnt::DBUS2_ACS_CNT_SPEC>;
729#[doc = "register description"]
730pub mod dbus2_acs_cnt;
731#[doc = "DBUS1_ACS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus1_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus1_acs_cnt`] module"]
732pub type DBUS1_ACS_CNT = crate::Reg<dbus1_acs_cnt::DBUS1_ACS_CNT_SPEC>;
733#[doc = "register description"]
734pub mod dbus1_acs_cnt;
735#[doc = "DBUS0_ACS_CNT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`dbus0_acs_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbus0_acs_cnt`] module"]
736pub type DBUS0_ACS_CNT = crate::Reg<dbus0_acs_cnt::DBUS0_ACS_CNT_SPEC>;
737#[doc = "register description"]
738pub mod dbus0_acs_cnt;
739#[doc = "CACHE_DBG_INT_ENA (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_dbg_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_dbg_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_dbg_int_ena`] module"]
740pub type CACHE_DBG_INT_ENA = crate::Reg<cache_dbg_int_ena::CACHE_DBG_INT_ENA_SPEC>;
741#[doc = "register description"]
742pub mod cache_dbg_int_ena;
743#[doc = "CACHE_DBG_INT_CLR (w) register accessor: register description\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_dbg_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_dbg_int_clr`] module"]
744pub type CACHE_DBG_INT_CLR = crate::Reg<cache_dbg_int_clr::CACHE_DBG_INT_CLR_SPEC>;
745#[doc = "register description"]
746pub mod cache_dbg_int_clr;
747#[doc = "CACHE_DBG_STATUS0 (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_dbg_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_dbg_status0`] module"]
748pub type CACHE_DBG_STATUS0 = crate::Reg<cache_dbg_status0::CACHE_DBG_STATUS0_SPEC>;
749#[doc = "register description"]
750pub mod cache_dbg_status0;
751#[doc = "CACHE_DBG_STATUS1 (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_dbg_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_dbg_status1`] module"]
752pub type CACHE_DBG_STATUS1 = crate::Reg<cache_dbg_status1::CACHE_DBG_STATUS1_SPEC>;
753#[doc = "register description"]
754pub mod cache_dbg_status1;
755#[doc = "PRO_CACHE_ACS_CNT_CLR (w) register accessor: register description\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_cache_acs_cnt_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_cache_acs_cnt_clr`] module"]
756pub type PRO_CACHE_ACS_CNT_CLR = crate::Reg<pro_cache_acs_cnt_clr::PRO_CACHE_ACS_CNT_CLR_SPEC>;
757#[doc = "register description"]
758pub mod pro_cache_acs_cnt_clr;
759#[doc = "PRO_DCACHE_REJECT_ST (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_reject_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_reject_st`] module"]
760pub type PRO_DCACHE_REJECT_ST = crate::Reg<pro_dcache_reject_st::PRO_DCACHE_REJECT_ST_SPEC>;
761#[doc = "register description"]
762pub mod pro_dcache_reject_st;
763#[doc = "PRO_DCACHE_REJECT_VADDR (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_reject_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_dcache_reject_vaddr`] module"]
764pub type PRO_DCACHE_REJECT_VADDR =
765    crate::Reg<pro_dcache_reject_vaddr::PRO_DCACHE_REJECT_VADDR_SPEC>;
766#[doc = "register description"]
767pub mod pro_dcache_reject_vaddr;
768#[doc = "PRO_ICACHE_REJECT_ST (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_reject_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_reject_st`] module"]
769pub type PRO_ICACHE_REJECT_ST = crate::Reg<pro_icache_reject_st::PRO_ICACHE_REJECT_ST_SPEC>;
770#[doc = "register description"]
771pub mod pro_icache_reject_st;
772#[doc = "PRO_ICACHE_REJECT_VADDR (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_reject_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_icache_reject_vaddr`] module"]
773pub type PRO_ICACHE_REJECT_VADDR =
774    crate::Reg<pro_icache_reject_vaddr::PRO_ICACHE_REJECT_VADDR_SPEC>;
775#[doc = "register description"]
776pub mod pro_icache_reject_vaddr;
777#[doc = "PRO_CACHE_MMU_FAULT_CONTENT (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_mmu_fault_content::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_cache_mmu_fault_content`] module"]
778pub type PRO_CACHE_MMU_FAULT_CONTENT =
779    crate::Reg<pro_cache_mmu_fault_content::PRO_CACHE_MMU_FAULT_CONTENT_SPEC>;
780#[doc = "register description"]
781pub mod pro_cache_mmu_fault_content;
782#[doc = "PRO_CACHE_MMU_FAULT_VADDR (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_mmu_fault_vaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_cache_mmu_fault_vaddr`] module"]
783pub type PRO_CACHE_MMU_FAULT_VADDR =
784    crate::Reg<pro_cache_mmu_fault_vaddr::PRO_CACHE_MMU_FAULT_VADDR_SPEC>;
785#[doc = "register description"]
786pub mod pro_cache_mmu_fault_vaddr;
787#[doc = "PRO_CACHE_WRAP_AROUND_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_wrap_around_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_cache_wrap_around_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_cache_wrap_around_ctrl`] module"]
788pub type PRO_CACHE_WRAP_AROUND_CTRL =
789    crate::Reg<pro_cache_wrap_around_ctrl::PRO_CACHE_WRAP_AROUND_CTRL_SPEC>;
790#[doc = "register description"]
791pub mod pro_cache_wrap_around_ctrl;
792#[doc = "PRO_CACHE_MMU_POWER_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_mmu_power_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_cache_mmu_power_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_cache_mmu_power_ctrl`] module"]
793pub type PRO_CACHE_MMU_POWER_CTRL =
794    crate::Reg<pro_cache_mmu_power_ctrl::PRO_CACHE_MMU_POWER_CTRL_SPEC>;
795#[doc = "register description"]
796pub mod pro_cache_mmu_power_ctrl;
797#[doc = "PRO_CACHE_STATE (r) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_cache_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_cache_state`] module"]
798pub type PRO_CACHE_STATE = crate::Reg<pro_cache_state::PRO_CACHE_STATE_SPEC>;
799#[doc = "register description"]
800pub mod pro_cache_state;
801#[doc = "CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_encrypt_decrypt_record_disable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_encrypt_decrypt_record_disable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_encrypt_decrypt_record_disable`] module"]
802pub type CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE =
803    crate::Reg<cache_encrypt_decrypt_record_disable::CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC>;
804#[doc = "register description"]
805pub mod cache_encrypt_decrypt_record_disable;
806#[doc = "CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_encrypt_decrypt_clk_force_on::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_encrypt_decrypt_clk_force_on::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_encrypt_decrypt_clk_force_on`] module"]
807pub type CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON =
808    crate::Reg<cache_encrypt_decrypt_clk_force_on::CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC>;
809#[doc = "register description"]
810pub mod cache_encrypt_decrypt_clk_force_on;
811#[doc = "CACHE_BRIDGE_ARBITER_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_bridge_arbiter_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_bridge_arbiter_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_bridge_arbiter_ctrl`] module"]
812pub type CACHE_BRIDGE_ARBITER_CTRL =
813    crate::Reg<cache_bridge_arbiter_ctrl::CACHE_BRIDGE_ARBITER_CTRL_SPEC>;
814#[doc = "register description"]
815pub mod cache_bridge_arbiter_ctrl;
816#[doc = "CACHE_PRELOAD_INT_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_preload_int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_preload_int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_preload_int_ctrl`] module"]
817pub type CACHE_PRELOAD_INT_CTRL = crate::Reg<cache_preload_int_ctrl::CACHE_PRELOAD_INT_CTRL_SPEC>;
818#[doc = "register description"]
819pub mod cache_preload_int_ctrl;
820#[doc = "CACHE_SYNC_INT_CTRL (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sync_int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_sync_int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_sync_int_ctrl`] module"]
821pub type CACHE_SYNC_INT_CTRL = crate::Reg<cache_sync_int_ctrl::CACHE_SYNC_INT_CTRL_SPEC>;
822#[doc = "register description"]
823pub mod cache_sync_int_ctrl;
824#[doc = "CACHE_CONF_MISC (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_conf_misc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_conf_misc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_conf_misc`] module"]
825pub type CACHE_CONF_MISC = crate::Reg<cache_conf_misc::CACHE_CONF_MISC_SPEC>;
826#[doc = "register description"]
827pub mod cache_conf_misc;
828#[doc = "CLOCK_GATE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
829pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
830#[doc = "register description"]
831pub mod clock_gate;
832#[doc = "PRO_EXTMEM_REG_DATE (rw) register accessor: register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_extmem_reg_date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_extmem_reg_date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pro_extmem_reg_date`] module"]
833pub type PRO_EXTMEM_REG_DATE = crate::Reg<pro_extmem_reg_date::PRO_EXTMEM_REG_DATE_SPEC>;
834#[doc = "register description"]
835pub mod pro_extmem_reg_date;
esp32s2/extmem.rs

esp32s2/
extmem.rs
