1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Field `CS_SETUP_TIME` reader - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state."]
6pub type CS_SETUP_TIME_R = crate::FieldReader<u16>;
7#[doc = "Field `CS_SETUP_TIME` writer - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state."]
8pub type CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
9#[doc = "Field `CS_HOLD_TIME` reader - delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state."]
10pub type CS_HOLD_TIME_R = crate::FieldReader<u16>;
11#[doc = "Field `CS_HOLD_TIME` writer - delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state."]
12pub type CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
13#[doc = "Field `CS_DELAY_MODE` reader - spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state."]
14pub type CS_DELAY_MODE_R = crate::FieldReader;
15#[doc = "Field `CS_DELAY_MODE` writer - spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state."]
16pub type CS_DELAY_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `CS_DELAY_NUM` reader - spi_cs signal is delayed by system clock cycles. Can be configured in CONF state."]
18pub type CS_DELAY_NUM_R = crate::FieldReader;
19#[doc = "Field `CS_DELAY_NUM` writer - spi_cs signal is delayed by system clock cycles. Can be configured in CONF state."]
20pub type CS_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21impl R {
22 #[doc = "Bits 0:12 - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state."]
23 #[inline(always)]
24 pub fn cs_setup_time(&self) -> CS_SETUP_TIME_R {
25 CS_SETUP_TIME_R::new((self.bits & 0x1fff) as u16)
26 }
27 #[doc = "Bits 13:25 - delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state."]
28 #[inline(always)]
29 pub fn cs_hold_time(&self) -> CS_HOLD_TIME_R {
30 CS_HOLD_TIME_R::new(((self.bits >> 13) & 0x1fff) as u16)
31 }
32 #[doc = "Bits 26:28 - spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state."]
33 #[inline(always)]
34 pub fn cs_delay_mode(&self) -> CS_DELAY_MODE_R {
35 CS_DELAY_MODE_R::new(((self.bits >> 26) & 7) as u8)
36 }
37 #[doc = "Bits 29:30 - spi_cs signal is delayed by system clock cycles. Can be configured in CONF state."]
38 #[inline(always)]
39 pub fn cs_delay_num(&self) -> CS_DELAY_NUM_R {
40 CS_DELAY_NUM_R::new(((self.bits >> 29) & 3) as u8)
41 }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46 f.debug_struct("CTRL2")
47 .field("cs_setup_time", &self.cs_setup_time())
48 .field("cs_hold_time", &self.cs_hold_time())
49 .field("cs_delay_mode", &self.cs_delay_mode())
50 .field("cs_delay_num", &self.cs_delay_num())
51 .finish()
52 }
53}
54impl W {
55 #[doc = "Bits 0:12 - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state."]
56 #[inline(always)]
57 pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<CTRL2_SPEC> {
58 CS_SETUP_TIME_W::new(self, 0)
59 }
60 #[doc = "Bits 13:25 - delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state."]
61 #[inline(always)]
62 pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<CTRL2_SPEC> {
63 CS_HOLD_TIME_W::new(self, 13)
64 }
65 #[doc = "Bits 26:28 - spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state."]
66 #[inline(always)]
67 pub fn cs_delay_mode(&mut self) -> CS_DELAY_MODE_W<CTRL2_SPEC> {
68 CS_DELAY_MODE_W::new(self, 26)
69 }
70 #[doc = "Bits 29:30 - spi_cs signal is delayed by system clock cycles. Can be configured in CONF state."]
71 #[inline(always)]
72 pub fn cs_delay_num(&mut self) -> CS_DELAY_NUM_W<CTRL2_SPEC> {
73 CS_DELAY_NUM_W::new(self, 29)
74 }
75}
76#[doc = "SPI control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct CTRL2_SPEC;
78impl crate::RegisterSpec for CTRL2_SPEC {
79 type Ux = u32;
80}
81#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
82impl crate::Readable for CTRL2_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
84impl crate::Writable for CTRL2_SPEC {
85 type Safety = crate::Unsafe;
86 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets CTRL2 to value 0x2000"]
90impl crate::Resettable for CTRL2_SPEC {
91 const RESET_VALUE: u32 = 0x2000;
92}