esp32s2/extmem/
pro_dcache_ctrl1.rs

1#[doc = "Register `PRO_DCACHE_CTRL1` reader"]
2pub type R = crate::R<PRO_DCACHE_CTRL1_SPEC>;
3#[doc = "Register `PRO_DCACHE_CTRL1` writer"]
4pub type W = crate::W<PRO_DCACHE_CTRL1_SPEC>;
5#[doc = "Field `PRO_DCACHE_MASK_BUS0` reader - The bit is used to disable dbus0, 0: enable, 1: disable"]
6pub type PRO_DCACHE_MASK_BUS0_R = crate::BitReader;
7#[doc = "Field `PRO_DCACHE_MASK_BUS0` writer - The bit is used to disable dbus0, 0: enable, 1: disable"]
8pub type PRO_DCACHE_MASK_BUS0_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_DCACHE_MASK_BUS1` reader - The bit is used to disable dbus1, 0: enable, 1: disable"]
10pub type PRO_DCACHE_MASK_BUS1_R = crate::BitReader;
11#[doc = "Field `PRO_DCACHE_MASK_BUS1` writer - The bit is used to disable dbus1, 0: enable, 1: disable"]
12pub type PRO_DCACHE_MASK_BUS1_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_DCACHE_MASK_BUS2` reader - The bit is used to disable dbus2, 0: enable, 1: disable"]
14pub type PRO_DCACHE_MASK_BUS2_R = crate::BitReader;
15#[doc = "Field `PRO_DCACHE_MASK_BUS2` writer - The bit is used to disable dbus2, 0: enable, 1: disable"]
16pub type PRO_DCACHE_MASK_BUS2_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - The bit is used to disable dbus0, 0: enable, 1: disable"]
19    #[inline(always)]
20    pub fn pro_dcache_mask_bus0(&self) -> PRO_DCACHE_MASK_BUS0_R {
21        PRO_DCACHE_MASK_BUS0_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - The bit is used to disable dbus1, 0: enable, 1: disable"]
24    #[inline(always)]
25    pub fn pro_dcache_mask_bus1(&self) -> PRO_DCACHE_MASK_BUS1_R {
26        PRO_DCACHE_MASK_BUS1_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - The bit is used to disable dbus2, 0: enable, 1: disable"]
29    #[inline(always)]
30    pub fn pro_dcache_mask_bus2(&self) -> PRO_DCACHE_MASK_BUS2_R {
31        PRO_DCACHE_MASK_BUS2_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("PRO_DCACHE_CTRL1")
38            .field("pro_dcache_mask_bus0", &self.pro_dcache_mask_bus0())
39            .field("pro_dcache_mask_bus1", &self.pro_dcache_mask_bus1())
40            .field("pro_dcache_mask_bus2", &self.pro_dcache_mask_bus2())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 0 - The bit is used to disable dbus0, 0: enable, 1: disable"]
46    #[inline(always)]
47    pub fn pro_dcache_mask_bus0(&mut self) -> PRO_DCACHE_MASK_BUS0_W<PRO_DCACHE_CTRL1_SPEC> {
48        PRO_DCACHE_MASK_BUS0_W::new(self, 0)
49    }
50    #[doc = "Bit 1 - The bit is used to disable dbus1, 0: enable, 1: disable"]
51    #[inline(always)]
52    pub fn pro_dcache_mask_bus1(&mut self) -> PRO_DCACHE_MASK_BUS1_W<PRO_DCACHE_CTRL1_SPEC> {
53        PRO_DCACHE_MASK_BUS1_W::new(self, 1)
54    }
55    #[doc = "Bit 2 - The bit is used to disable dbus2, 0: enable, 1: disable"]
56    #[inline(always)]
57    pub fn pro_dcache_mask_bus2(&mut self) -> PRO_DCACHE_MASK_BUS2_W<PRO_DCACHE_CTRL1_SPEC> {
58        PRO_DCACHE_MASK_BUS2_W::new(self, 2)
59    }
60}
61#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dcache_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dcache_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct PRO_DCACHE_CTRL1_SPEC;
63impl crate::RegisterSpec for PRO_DCACHE_CTRL1_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`pro_dcache_ctrl1::R`](R) reader structure"]
67impl crate::Readable for PRO_DCACHE_CTRL1_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`pro_dcache_ctrl1::W`](W) writer structure"]
69impl crate::Writable for PRO_DCACHE_CTRL1_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets PRO_DCACHE_CTRL1 to value 0x07"]
75impl crate::Resettable for PRO_DCACHE_CTRL1_SPEC {
76    const RESET_VALUE: u32 = 0x07;
77}
esp32s2/extmem/pro_dcache_ctrl1.rs

esp32s2/extmem/
pro_dcache_ctrl1.rs
