#[repr(C)]pub struct RegisterBlock { /* private fields */ }
Expand description
Register block
Implementations§
Source§impl RegisterBlock
impl RegisterBlock
Sourcepub const fn rom_ctrl_0(&self) -> &ROM_CTRL_0
pub const fn rom_ctrl_0(&self) -> &ROM_CTRL_0
0x00 - System ROM configuration register 0
Sourcepub const fn rom_ctrl_1(&self) -> &ROM_CTRL_1
pub const fn rom_ctrl_1(&self) -> &ROM_CTRL_1
0x04 - System ROM configuration register 1
Sourcepub const fn sram_ctrl_0(&self) -> &SRAM_CTRL_0
pub const fn sram_ctrl_0(&self) -> &SRAM_CTRL_0
0x08 - System SRAM configuration register 0
Sourcepub const fn sram_ctrl_1(&self) -> &SRAM_CTRL_1
pub const fn sram_ctrl_1(&self) -> &SRAM_CTRL_1
0x0c - System SRAM configuration register 1
Sourcepub const fn cpu_peri_clk_en(&self) -> &CPU_PERI_CLK_EN
pub const fn cpu_peri_clk_en(&self) -> &CPU_PERI_CLK_EN
0x10 - CPU peripheral clock enable register
Sourcepub const fn cpu_peri_rst_en(&self) -> &CPU_PERI_RST_EN
pub const fn cpu_peri_rst_en(&self) -> &CPU_PERI_RST_EN
0x14 - CPU peripheral reset register
Sourcepub const fn cpu_per_conf(&self) -> &CPU_PER_CONF
pub const fn cpu_per_conf(&self) -> &CPU_PER_CONF
0x18 - CPU peripheral clock configuration register
Sourcepub const fn jtag_ctrl_0(&self) -> &JTAG_CTRL_0
pub const fn jtag_ctrl_0(&self) -> &JTAG_CTRL_0
0x1c - JTAG configuration register 0
Sourcepub const fn jtag_ctrl_1(&self) -> &JTAG_CTRL_1
pub const fn jtag_ctrl_1(&self) -> &JTAG_CTRL_1
0x20 - JTAG configuration register 1
Sourcepub const fn jtag_ctrl_2(&self) -> &JTAG_CTRL_2
pub const fn jtag_ctrl_2(&self) -> &JTAG_CTRL_2
0x24 - JTAG configuration register 2
Sourcepub const fn jtag_ctrl_3(&self) -> &JTAG_CTRL_3
pub const fn jtag_ctrl_3(&self) -> &JTAG_CTRL_3
0x28 - JTAG configuration register 3
Sourcepub const fn jtag_ctrl_4(&self) -> &JTAG_CTRL_4
pub const fn jtag_ctrl_4(&self) -> &JTAG_CTRL_4
0x2c - JTAG configuration register 4
Sourcepub const fn jtag_ctrl_5(&self) -> &JTAG_CTRL_5
pub const fn jtag_ctrl_5(&self) -> &JTAG_CTRL_5
0x30 - JTAG configuration register 5
Sourcepub const fn jtag_ctrl_6(&self) -> &JTAG_CTRL_6
pub const fn jtag_ctrl_6(&self) -> &JTAG_CTRL_6
0x34 - JTAG configuration register 6
Sourcepub const fn jtag_ctrl_7(&self) -> &JTAG_CTRL_7
pub const fn jtag_ctrl_7(&self) -> &JTAG_CTRL_7
0x38 - JTAG configuration register 7
Sourcepub const fn mem_pd_mask(&self) -> &MEM_PD_MASK
pub const fn mem_pd_mask(&self) -> &MEM_PD_MASK
0x3c - Memory power-related controlling register (under low-sleep)
Sourcepub const fn perip_clk_en0(&self) -> &PERIP_CLK_EN0
pub const fn perip_clk_en0(&self) -> &PERIP_CLK_EN0
0x40 - System peripheral clock (for hardware accelerators) enable register
Sourcepub const fn perip_clk_en1(&self) -> &PERIP_CLK_EN1
pub const fn perip_clk_en1(&self) -> &PERIP_CLK_EN1
0x44 - System peripheral clock (for hardware accelerators) enable register 1
Sourcepub const fn perip_rst_en0(&self) -> &PERIP_RST_EN0
pub const fn perip_rst_en0(&self) -> &PERIP_RST_EN0
0x48 - System peripheral (hardware accelerators) reset register 0
Sourcepub const fn perip_rst_en1(&self) -> &PERIP_RST_EN1
pub const fn perip_rst_en1(&self) -> &PERIP_RST_EN1
0x4c - System peripheral (hardware accelerators) reset register 1
Sourcepub const fn lpck_div_int(&self) -> &LPCK_DIV_INT
pub const fn lpck_div_int(&self) -> &LPCK_DIV_INT
0x50 - Low power clock divider integer register
Sourcepub const fn bt_lpck_div_frac(&self) -> &BT_LPCK_DIV_FRAC
pub const fn bt_lpck_div_frac(&self) -> &BT_LPCK_DIV_FRAC
0x54 - Divider fraction configuration register for low-power clock
Sourcepub const fn cpu_intr_from_cpu_0(&self) -> &CPU_INTR_FROM_CPU_0
pub const fn cpu_intr_from_cpu_0(&self) -> &CPU_INTR_FROM_CPU_0
0x58 - CPU interrupt controlling register 0
Sourcepub const fn cpu_intr_from_cpu_1(&self) -> &CPU_INTR_FROM_CPU_1
pub const fn cpu_intr_from_cpu_1(&self) -> &CPU_INTR_FROM_CPU_1
0x5c - CPU interrupt controlling register 1
Sourcepub const fn cpu_intr_from_cpu_2(&self) -> &CPU_INTR_FROM_CPU_2
pub const fn cpu_intr_from_cpu_2(&self) -> &CPU_INTR_FROM_CPU_2
0x60 - CPU interrupt controlling register 2
Sourcepub const fn cpu_intr_from_cpu_3(&self) -> &CPU_INTR_FROM_CPU_3
pub const fn cpu_intr_from_cpu_3(&self) -> &CPU_INTR_FROM_CPU_3
0x64 - CPU interrupt controlling register 3
Sourcepub const fn rsa_pd_ctrl(&self) -> &RSA_PD_CTRL
pub const fn rsa_pd_ctrl(&self) -> &RSA_PD_CTRL
0x68 - RSA memory remapping register
Sourcepub const fn bustoextmem_ena(&self) -> &BUSTOEXTMEM_ENA
pub const fn bustoextmem_ena(&self) -> &BUSTOEXTMEM_ENA
0x6c - EDMA enable register
Sourcepub const fn cache_control(&self) -> &CACHE_CONTROL
pub const fn cache_control(&self) -> &CACHE_CONTROL
0x70 - Cache control register
Sourcepub const fn external_device_encrypt_decrypt_control(
&self,
) -> &EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL
pub const fn external_device_encrypt_decrypt_control( &self, ) -> &EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL
0x74 - External memory encrypt and decrypt controlling register
Sourcepub const fn rtc_fastmem_config(&self) -> &RTC_FASTMEM_CONFIG
pub const fn rtc_fastmem_config(&self) -> &RTC_FASTMEM_CONFIG
0x78 - RTC fast memory configuration register
Sourcepub const fn rtc_fastmem_crc(&self) -> &RTC_FASTMEM_CRC
pub const fn rtc_fastmem_crc(&self) -> &RTC_FASTMEM_CRC
0x7c - RTC fast memory CRC controlling register
Sourcepub const fn redundant_eco_ctrl(&self) -> &REDUNDANT_ECO_CTRL
pub const fn redundant_eco_ctrl(&self) -> &REDUNDANT_ECO_CTRL
0x80 - Redundant ECO control register
Sourcepub const fn clock_gate(&self) -> &CLOCK_GATE
pub const fn clock_gate(&self) -> &CLOCK_GATE
0x84 - Clock gate control register
Sourcepub const fn sram_ctrl_2(&self) -> &SRAM_CTRL_2
pub const fn sram_ctrl_2(&self) -> &SRAM_CTRL_2
0x88 - System SRAM configuration register 2
Sourcepub const fn sysclk_conf(&self) -> &SYSCLK_CONF
pub const fn sysclk_conf(&self) -> &SYSCLK_CONF
0x8c - SoC clock configuration register