1#[doc = "Register `OTG_CONF` reader"]
2pub type R = crate::R<OTG_CONF_SPEC>;
3#[doc = "Register `OTG_CONF` writer"]
4pub type W = crate::W<OTG_CONF_SPEC>;
5#[doc = "Field `SRP_SESSEND_OVERRIDE` reader - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
6pub type SRP_SESSEND_OVERRIDE_R = crate::BitReader;
7#[doc = "Field `SRP_SESSEND_OVERRIDE` writer - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
8pub type SRP_SESSEND_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SRP_SESSEND_VALUE` reader - Software over-ride value of srp session end signal."]
10pub type SRP_SESSEND_VALUE_R = crate::BitReader;
11#[doc = "Field `SRP_SESSEND_VALUE` writer - Software over-ride value of srp session end signal."]
12pub type SRP_SESSEND_VALUE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PHY_SEL` reader - Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY."]
14pub type PHY_SEL_R = crate::BitReader;
15#[doc = "Field `PHY_SEL` writer - Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY."]
16pub type PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DFIFO_FORCE_PD` reader - Force the dfifo to go into low power mode. The data in dfifo will not lost."]
18pub type DFIFO_FORCE_PD_R = crate::BitReader;
19#[doc = "Field `DFIFO_FORCE_PD` writer - Force the dfifo to go into low power mode. The data in dfifo will not lost."]
20pub type DFIFO_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DBNCE_FLTR_BYPASS` reader - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"]
22pub type DBNCE_FLTR_BYPASS_R = crate::BitReader;
23#[doc = "Field `DBNCE_FLTR_BYPASS` writer - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"]
24pub type DBNCE_FLTR_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `EXCHG_PINS_OVERRIDE` reader - Enable software controlle USB D+ D- exchange"]
26pub type EXCHG_PINS_OVERRIDE_R = crate::BitReader;
27#[doc = "Field `EXCHG_PINS_OVERRIDE` writer - Enable software controlle USB D+ D- exchange"]
28pub type EXCHG_PINS_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `EXCHG_PINS` reader - USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-"]
30pub type EXCHG_PINS_R = crate::BitReader;
31#[doc = "Field `EXCHG_PINS` writer - USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-"]
32pub type EXCHG_PINS_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `VREFH` reader - Control single-end input high threshold,1.76V to 2V, step 80mV"]
34pub type VREFH_R = crate::FieldReader;
35#[doc = "Field `VREFH` writer - Control single-end input high threshold,1.76V to 2V, step 80mV"]
36pub type VREFH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `VREFL` reader - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
38pub type VREFL_R = crate::FieldReader;
39#[doc = "Field `VREFL` writer - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
40pub type VREFL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `VREF_OVERRIDE` reader - Enable software controlle input threshold"]
42pub type VREF_OVERRIDE_R = crate::BitReader;
43#[doc = "Field `VREF_OVERRIDE` writer - Enable software controlle input threshold"]
44pub type VREF_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `PAD_PULL_OVERRIDE` reader - Enable software controlle USB D+ D- pullup pulldown"]
46pub type PAD_PULL_OVERRIDE_R = crate::BitReader;
47#[doc = "Field `PAD_PULL_OVERRIDE` writer - Enable software controlle USB D+ D- pullup pulldown"]
48pub type PAD_PULL_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `DP_PULLUP` reader - Controlle USB D+ pullup"]
50pub type DP_PULLUP_R = crate::BitReader;
51#[doc = "Field `DP_PULLUP` writer - Controlle USB D+ pullup"]
52pub type DP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `DP_PULLDOWN` reader - Controlle USB D+ pulldown"]
54pub type DP_PULLDOWN_R = crate::BitReader;
55#[doc = "Field `DP_PULLDOWN` writer - Controlle USB D+ pulldown"]
56pub type DP_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `DM_PULLUP` reader - Controlle USB D+ pullup"]
58pub type DM_PULLUP_R = crate::BitReader;
59#[doc = "Field `DM_PULLUP` writer - Controlle USB D+ pullup"]
60pub type DM_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `DM_PULLDOWN` reader - Controlle USB D+ pulldown"]
62pub type DM_PULLDOWN_R = crate::BitReader;
63#[doc = "Field `DM_PULLDOWN` writer - Controlle USB D+ pulldown"]
64pub type DM_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `PULLUP_VALUE` reader - Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K."]
66pub type PULLUP_VALUE_R = crate::BitReader;
67#[doc = "Field `PULLUP_VALUE` writer - Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K."]
68pub type PULLUP_VALUE_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `USB_PAD_ENABLE` reader - Enable USB pad function"]
70pub type USB_PAD_ENABLE_R = crate::BitReader;
71#[doc = "Field `USB_PAD_ENABLE` writer - Enable USB pad function"]
72pub type USB_PAD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `AHB_CLK_FORCE_ON` reader - Force ahb clock always on"]
74pub type AHB_CLK_FORCE_ON_R = crate::BitReader;
75#[doc = "Field `AHB_CLK_FORCE_ON` writer - Force ahb clock always on"]
76pub type AHB_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `PHY_CLK_FORCE_ON` reader - Force phy clock always on"]
78pub type PHY_CLK_FORCE_ON_R = crate::BitReader;
79#[doc = "Field `PHY_CLK_FORCE_ON` writer - Force phy clock always on"]
80pub type PHY_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `PHY_TX_EDGE_SEL` reader - Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge."]
82pub type PHY_TX_EDGE_SEL_R = crate::BitReader;
83#[doc = "Field `PHY_TX_EDGE_SEL` writer - Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge."]
84pub type PHY_TX_EDGE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `DFIFO_FORCE_PU` reader - Disable the dfifo to go into low power mode. The data in dfifo will not lost."]
86pub type DFIFO_FORCE_PU_R = crate::BitReader;
87#[doc = "Field `DFIFO_FORCE_PU` writer - Disable the dfifo to go into low power mode. The data in dfifo will not lost."]
88pub type DFIFO_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `CLK_EN` reader - Disable auto clock gating of CSR registers"]
90pub type CLK_EN_R = crate::BitReader;
91#[doc = "Field `CLK_EN` writer - Disable auto clock gating of CSR registers"]
92pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
93impl R {
94 #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
95 #[inline(always)]
96 pub fn srp_sessend_override(&self) -> SRP_SESSEND_OVERRIDE_R {
97 SRP_SESSEND_OVERRIDE_R::new((self.bits & 1) != 0)
98 }
99 #[doc = "Bit 1 - Software over-ride value of srp session end signal."]
100 #[inline(always)]
101 pub fn srp_sessend_value(&self) -> SRP_SESSEND_VALUE_R {
102 SRP_SESSEND_VALUE_R::new(((self.bits >> 1) & 1) != 0)
103 }
104 #[doc = "Bit 2 - Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY."]
105 #[inline(always)]
106 pub fn phy_sel(&self) -> PHY_SEL_R {
107 PHY_SEL_R::new(((self.bits >> 2) & 1) != 0)
108 }
109 #[doc = "Bit 3 - Force the dfifo to go into low power mode. The data in dfifo will not lost."]
110 #[inline(always)]
111 pub fn dfifo_force_pd(&self) -> DFIFO_FORCE_PD_R {
112 DFIFO_FORCE_PD_R::new(((self.bits >> 3) & 1) != 0)
113 }
114 #[doc = "Bit 4 - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"]
115 #[inline(always)]
116 pub fn dbnce_fltr_bypass(&self) -> DBNCE_FLTR_BYPASS_R {
117 DBNCE_FLTR_BYPASS_R::new(((self.bits >> 4) & 1) != 0)
118 }
119 #[doc = "Bit 5 - Enable software controlle USB D+ D- exchange"]
120 #[inline(always)]
121 pub fn exchg_pins_override(&self) -> EXCHG_PINS_OVERRIDE_R {
122 EXCHG_PINS_OVERRIDE_R::new(((self.bits >> 5) & 1) != 0)
123 }
124 #[doc = "Bit 6 - USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-"]
125 #[inline(always)]
126 pub fn exchg_pins(&self) -> EXCHG_PINS_R {
127 EXCHG_PINS_R::new(((self.bits >> 6) & 1) != 0)
128 }
129 #[doc = "Bits 7:8 - Control single-end input high threshold,1.76V to 2V, step 80mV"]
130 #[inline(always)]
131 pub fn vrefh(&self) -> VREFH_R {
132 VREFH_R::new(((self.bits >> 7) & 3) as u8)
133 }
134 #[doc = "Bits 9:10 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
135 #[inline(always)]
136 pub fn vrefl(&self) -> VREFL_R {
137 VREFL_R::new(((self.bits >> 9) & 3) as u8)
138 }
139 #[doc = "Bit 11 - Enable software controlle input threshold"]
140 #[inline(always)]
141 pub fn vref_override(&self) -> VREF_OVERRIDE_R {
142 VREF_OVERRIDE_R::new(((self.bits >> 11) & 1) != 0)
143 }
144 #[doc = "Bit 12 - Enable software controlle USB D+ D- pullup pulldown"]
145 #[inline(always)]
146 pub fn pad_pull_override(&self) -> PAD_PULL_OVERRIDE_R {
147 PAD_PULL_OVERRIDE_R::new(((self.bits >> 12) & 1) != 0)
148 }
149 #[doc = "Bit 13 - Controlle USB D+ pullup"]
150 #[inline(always)]
151 pub fn dp_pullup(&self) -> DP_PULLUP_R {
152 DP_PULLUP_R::new(((self.bits >> 13) & 1) != 0)
153 }
154 #[doc = "Bit 14 - Controlle USB D+ pulldown"]
155 #[inline(always)]
156 pub fn dp_pulldown(&self) -> DP_PULLDOWN_R {
157 DP_PULLDOWN_R::new(((self.bits >> 14) & 1) != 0)
158 }
159 #[doc = "Bit 15 - Controlle USB D+ pullup"]
160 #[inline(always)]
161 pub fn dm_pullup(&self) -> DM_PULLUP_R {
162 DM_PULLUP_R::new(((self.bits >> 15) & 1) != 0)
163 }
164 #[doc = "Bit 16 - Controlle USB D+ pulldown"]
165 #[inline(always)]
166 pub fn dm_pulldown(&self) -> DM_PULLDOWN_R {
167 DM_PULLDOWN_R::new(((self.bits >> 16) & 1) != 0)
168 }
169 #[doc = "Bit 17 - Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K."]
170 #[inline(always)]
171 pub fn pullup_value(&self) -> PULLUP_VALUE_R {
172 PULLUP_VALUE_R::new(((self.bits >> 17) & 1) != 0)
173 }
174 #[doc = "Bit 18 - Enable USB pad function"]
175 #[inline(always)]
176 pub fn usb_pad_enable(&self) -> USB_PAD_ENABLE_R {
177 USB_PAD_ENABLE_R::new(((self.bits >> 18) & 1) != 0)
178 }
179 #[doc = "Bit 19 - Force ahb clock always on"]
180 #[inline(always)]
181 pub fn ahb_clk_force_on(&self) -> AHB_CLK_FORCE_ON_R {
182 AHB_CLK_FORCE_ON_R::new(((self.bits >> 19) & 1) != 0)
183 }
184 #[doc = "Bit 20 - Force phy clock always on"]
185 #[inline(always)]
186 pub fn phy_clk_force_on(&self) -> PHY_CLK_FORCE_ON_R {
187 PHY_CLK_FORCE_ON_R::new(((self.bits >> 20) & 1) != 0)
188 }
189 #[doc = "Bit 21 - Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge."]
190 #[inline(always)]
191 pub fn phy_tx_edge_sel(&self) -> PHY_TX_EDGE_SEL_R {
192 PHY_TX_EDGE_SEL_R::new(((self.bits >> 21) & 1) != 0)
193 }
194 #[doc = "Bit 22 - Disable the dfifo to go into low power mode. The data in dfifo will not lost."]
195 #[inline(always)]
196 pub fn dfifo_force_pu(&self) -> DFIFO_FORCE_PU_R {
197 DFIFO_FORCE_PU_R::new(((self.bits >> 22) & 1) != 0)
198 }
199 #[doc = "Bit 31 - Disable auto clock gating of CSR registers"]
200 #[inline(always)]
201 pub fn clk_en(&self) -> CLK_EN_R {
202 CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
203 }
204}
205#[cfg(feature = "impl-register-debug")]
206impl core::fmt::Debug for R {
207 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
208 f.debug_struct("OTG_CONF")
209 .field("srp_sessend_override", &self.srp_sessend_override())
210 .field("srp_sessend_value", &self.srp_sessend_value())
211 .field("phy_sel", &self.phy_sel())
212 .field("dfifo_force_pd", &self.dfifo_force_pd())
213 .field("dbnce_fltr_bypass", &self.dbnce_fltr_bypass())
214 .field("exchg_pins_override", &self.exchg_pins_override())
215 .field("exchg_pins", &self.exchg_pins())
216 .field("vrefh", &self.vrefh())
217 .field("vrefl", &self.vrefl())
218 .field("vref_override", &self.vref_override())
219 .field("pad_pull_override", &self.pad_pull_override())
220 .field("dp_pullup", &self.dp_pullup())
221 .field("dp_pulldown", &self.dp_pulldown())
222 .field("dm_pullup", &self.dm_pullup())
223 .field("dm_pulldown", &self.dm_pulldown())
224 .field("pullup_value", &self.pullup_value())
225 .field("usb_pad_enable", &self.usb_pad_enable())
226 .field("ahb_clk_force_on", &self.ahb_clk_force_on())
227 .field("phy_clk_force_on", &self.phy_clk_force_on())
228 .field("phy_tx_edge_sel", &self.phy_tx_edge_sel())
229 .field("dfifo_force_pu", &self.dfifo_force_pu())
230 .field("clk_en", &self.clk_en())
231 .finish()
232 }
233}
234impl W {
235 #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
236 #[inline(always)]
237 pub fn srp_sessend_override(&mut self) -> SRP_SESSEND_OVERRIDE_W<OTG_CONF_SPEC> {
238 SRP_SESSEND_OVERRIDE_W::new(self, 0)
239 }
240 #[doc = "Bit 1 - Software over-ride value of srp session end signal."]
241 #[inline(always)]
242 pub fn srp_sessend_value(&mut self) -> SRP_SESSEND_VALUE_W<OTG_CONF_SPEC> {
243 SRP_SESSEND_VALUE_W::new(self, 1)
244 }
245 #[doc = "Bit 2 - Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY."]
246 #[inline(always)]
247 pub fn phy_sel(&mut self) -> PHY_SEL_W<OTG_CONF_SPEC> {
248 PHY_SEL_W::new(self, 2)
249 }
250 #[doc = "Bit 3 - Force the dfifo to go into low power mode. The data in dfifo will not lost."]
251 #[inline(always)]
252 pub fn dfifo_force_pd(&mut self) -> DFIFO_FORCE_PD_W<OTG_CONF_SPEC> {
253 DFIFO_FORCE_PD_W::new(self, 3)
254 }
255 #[doc = "Bit 4 - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"]
256 #[inline(always)]
257 pub fn dbnce_fltr_bypass(&mut self) -> DBNCE_FLTR_BYPASS_W<OTG_CONF_SPEC> {
258 DBNCE_FLTR_BYPASS_W::new(self, 4)
259 }
260 #[doc = "Bit 5 - Enable software controlle USB D+ D- exchange"]
261 #[inline(always)]
262 pub fn exchg_pins_override(&mut self) -> EXCHG_PINS_OVERRIDE_W<OTG_CONF_SPEC> {
263 EXCHG_PINS_OVERRIDE_W::new(self, 5)
264 }
265 #[doc = "Bit 6 - USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-"]
266 #[inline(always)]
267 pub fn exchg_pins(&mut self) -> EXCHG_PINS_W<OTG_CONF_SPEC> {
268 EXCHG_PINS_W::new(self, 6)
269 }
270 #[doc = "Bits 7:8 - Control single-end input high threshold,1.76V to 2V, step 80mV"]
271 #[inline(always)]
272 pub fn vrefh(&mut self) -> VREFH_W<OTG_CONF_SPEC> {
273 VREFH_W::new(self, 7)
274 }
275 #[doc = "Bits 9:10 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
276 #[inline(always)]
277 pub fn vrefl(&mut self) -> VREFL_W<OTG_CONF_SPEC> {
278 VREFL_W::new(self, 9)
279 }
280 #[doc = "Bit 11 - Enable software controlle input threshold"]
281 #[inline(always)]
282 pub fn vref_override(&mut self) -> VREF_OVERRIDE_W<OTG_CONF_SPEC> {
283 VREF_OVERRIDE_W::new(self, 11)
284 }
285 #[doc = "Bit 12 - Enable software controlle USB D+ D- pullup pulldown"]
286 #[inline(always)]
287 pub fn pad_pull_override(&mut self) -> PAD_PULL_OVERRIDE_W<OTG_CONF_SPEC> {
288 PAD_PULL_OVERRIDE_W::new(self, 12)
289 }
290 #[doc = "Bit 13 - Controlle USB D+ pullup"]
291 #[inline(always)]
292 pub fn dp_pullup(&mut self) -> DP_PULLUP_W<OTG_CONF_SPEC> {
293 DP_PULLUP_W::new(self, 13)
294 }
295 #[doc = "Bit 14 - Controlle USB D+ pulldown"]
296 #[inline(always)]
297 pub fn dp_pulldown(&mut self) -> DP_PULLDOWN_W<OTG_CONF_SPEC> {
298 DP_PULLDOWN_W::new(self, 14)
299 }
300 #[doc = "Bit 15 - Controlle USB D+ pullup"]
301 #[inline(always)]
302 pub fn dm_pullup(&mut self) -> DM_PULLUP_W<OTG_CONF_SPEC> {
303 DM_PULLUP_W::new(self, 15)
304 }
305 #[doc = "Bit 16 - Controlle USB D+ pulldown"]
306 #[inline(always)]
307 pub fn dm_pulldown(&mut self) -> DM_PULLDOWN_W<OTG_CONF_SPEC> {
308 DM_PULLDOWN_W::new(self, 16)
309 }
310 #[doc = "Bit 17 - Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K."]
311 #[inline(always)]
312 pub fn pullup_value(&mut self) -> PULLUP_VALUE_W<OTG_CONF_SPEC> {
313 PULLUP_VALUE_W::new(self, 17)
314 }
315 #[doc = "Bit 18 - Enable USB pad function"]
316 #[inline(always)]
317 pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<OTG_CONF_SPEC> {
318 USB_PAD_ENABLE_W::new(self, 18)
319 }
320 #[doc = "Bit 19 - Force ahb clock always on"]
321 #[inline(always)]
322 pub fn ahb_clk_force_on(&mut self) -> AHB_CLK_FORCE_ON_W<OTG_CONF_SPEC> {
323 AHB_CLK_FORCE_ON_W::new(self, 19)
324 }
325 #[doc = "Bit 20 - Force phy clock always on"]
326 #[inline(always)]
327 pub fn phy_clk_force_on(&mut self) -> PHY_CLK_FORCE_ON_W<OTG_CONF_SPEC> {
328 PHY_CLK_FORCE_ON_W::new(self, 20)
329 }
330 #[doc = "Bit 21 - Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge."]
331 #[inline(always)]
332 pub fn phy_tx_edge_sel(&mut self) -> PHY_TX_EDGE_SEL_W<OTG_CONF_SPEC> {
333 PHY_TX_EDGE_SEL_W::new(self, 21)
334 }
335 #[doc = "Bit 22 - Disable the dfifo to go into low power mode. The data in dfifo will not lost."]
336 #[inline(always)]
337 pub fn dfifo_force_pu(&mut self) -> DFIFO_FORCE_PU_W<OTG_CONF_SPEC> {
338 DFIFO_FORCE_PU_W::new(self, 22)
339 }
340 #[doc = "Bit 31 - Disable auto clock gating of CSR registers"]
341 #[inline(always)]
342 pub fn clk_en(&mut self) -> CLK_EN_W<OTG_CONF_SPEC> {
343 CLK_EN_W::new(self, 31)
344 }
345}
346#[doc = "USB OTG Wrapper Configure Register\n\nYou can [`read`](crate::Reg::read) this register and get [`otg_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otg_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
347pub struct OTG_CONF_SPEC;
348impl crate::RegisterSpec for OTG_CONF_SPEC {
349 type Ux = u32;
350}
351#[doc = "`read()` method returns [`otg_conf::R`](R) reader structure"]
352impl crate::Readable for OTG_CONF_SPEC {}
353#[doc = "`write(|w| ..)` method takes [`otg_conf::W`](W) writer structure"]
354impl crate::Writable for OTG_CONF_SPEC {
355 type Safety = crate::Unsafe;
356 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
357 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
358}
359#[doc = "`reset()` method sets OTG_CONF to value 0x001c_0000"]
360impl crate::Resettable for OTG_CONF_SPEC {
361 const RESET_VALUE: u32 = 0x001c_0000;
362}