esp32s2/rtc_cntl/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `SLP_WAKEUP` writer - Clears the interrupt triggered when the chip wakes up from sleep."]
4pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `SLP_REJECT` writer - Clears the interrupt triggered when the chip rejects to go to sleep."]
6pub type SLP_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `SDIO_IDLE` writer - Clears the interrupt triggered when the SDIO idles."]
8pub type SDIO_IDLE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `WDT` writer - Enables the RTC watchdog interrupt."]
10pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `TOUCH_SCAN_DONE` writer - Clears the interrupt triggered upon the completion of a touch scanning."]
12pub type TOUCH_SCAN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ULP_CP` writer - Enables the ULP co-processor interrupt."]
14pub type ULP_CP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `TOUCH_DONE` writer - Clears the interrupt triggered upon the completion of a single touch."]
16pub type TOUCH_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TOUCH_ACTIVE` writer - Clears the interrupt triggered when a touch is detected."]
18pub type TOUCH_ACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `TOUCH_INACTIVE` writer - Clears the interrupt triggered when a touch is released."]
20pub type TOUCH_INACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `BROWN_OUT` writer - Clears the brown out interrupt."]
22pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `MAIN_TIMER` writer - Clears the RTC main timer interrupt."]
24pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `SARADC1` writer - Clears the SAR ADC 1 interrupt."]
26pub type SARADC1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `TSENS` writer - Clears the touch sensor interrupt."]
28pub type TSENS_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `COCPU` writer - Clears the ULP-RISCV interrupt."]
30pub type COCPU_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SARADC2` writer - Clears the SAR ADC 2 interrupt."]
32pub type SARADC2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `SWD` writer - Clears the super watchdog interrupt."]
34pub type SWD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `XTAL32K_DEAD` writer - Clears the interrupt triggered when the 32 kHz crystal is dead."]
36pub type XTAL32K_DEAD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `COCPU_TRAP` writer - Clears the interrupt triggered when the ULP-RISCV is trapped."]
38pub type COCPU_TRAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `TOUCH_TIMEOUT` writer - Clears the interrupt triggered when touch sensor times out."]
40pub type TOUCH_TIMEOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `GLITCH_DET` writer - Clears the interrupt triggered when a glitch is detected."]
42pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
45    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
46        write!(f, "(not readable)")
47    }
48}
49impl W {
50    #[doc = "Bit 0 - Clears the interrupt triggered when the chip wakes up from sleep."]
51    #[inline(always)]
52    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
53        SLP_WAKEUP_W::new(self, 0)
54    }
55    #[doc = "Bit 1 - Clears the interrupt triggered when the chip rejects to go to sleep."]
56    #[inline(always)]
57    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
58        SLP_REJECT_W::new(self, 1)
59    }
60    #[doc = "Bit 2 - Clears the interrupt triggered when the SDIO idles."]
61    #[inline(always)]
62    pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_CLR_SPEC> {
63        SDIO_IDLE_W::new(self, 2)
64    }
65    #[doc = "Bit 3 - Enables the RTC watchdog interrupt."]
66    #[inline(always)]
67    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
68        WDT_W::new(self, 3)
69    }
70    #[doc = "Bit 4 - Clears the interrupt triggered upon the completion of a touch scanning."]
71    #[inline(always)]
72    pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_CLR_SPEC> {
73        TOUCH_SCAN_DONE_W::new(self, 4)
74    }
75    #[doc = "Bit 5 - Enables the ULP co-processor interrupt."]
76    #[inline(always)]
77    pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_CLR_SPEC> {
78        ULP_CP_W::new(self, 5)
79    }
80    #[doc = "Bit 6 - Clears the interrupt triggered upon the completion of a single touch."]
81    #[inline(always)]
82    pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_CLR_SPEC> {
83        TOUCH_DONE_W::new(self, 6)
84    }
85    #[doc = "Bit 7 - Clears the interrupt triggered when a touch is detected."]
86    #[inline(always)]
87    pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_CLR_SPEC> {
88        TOUCH_ACTIVE_W::new(self, 7)
89    }
90    #[doc = "Bit 8 - Clears the interrupt triggered when a touch is released."]
91    #[inline(always)]
92    pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_CLR_SPEC> {
93        TOUCH_INACTIVE_W::new(self, 8)
94    }
95    #[doc = "Bit 9 - Clears the brown out interrupt."]
96    #[inline(always)]
97    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
98        BROWN_OUT_W::new(self, 9)
99    }
100    #[doc = "Bit 10 - Clears the RTC main timer interrupt."]
101    #[inline(always)]
102    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
103        MAIN_TIMER_W::new(self, 10)
104    }
105    #[doc = "Bit 11 - Clears the SAR ADC 1 interrupt."]
106    #[inline(always)]
107    pub fn saradc1(&mut self) -> SARADC1_W<INT_CLR_SPEC> {
108        SARADC1_W::new(self, 11)
109    }
110    #[doc = "Bit 12 - Clears the touch sensor interrupt."]
111    #[inline(always)]
112    pub fn tsens(&mut self) -> TSENS_W<INT_CLR_SPEC> {
113        TSENS_W::new(self, 12)
114    }
115    #[doc = "Bit 13 - Clears the ULP-RISCV interrupt."]
116    #[inline(always)]
117    pub fn cocpu(&mut self) -> COCPU_W<INT_CLR_SPEC> {
118        COCPU_W::new(self, 13)
119    }
120    #[doc = "Bit 14 - Clears the SAR ADC 2 interrupt."]
121    #[inline(always)]
122    pub fn saradc2(&mut self) -> SARADC2_W<INT_CLR_SPEC> {
123        SARADC2_W::new(self, 14)
124    }
125    #[doc = "Bit 15 - Clears the super watchdog interrupt."]
126    #[inline(always)]
127    pub fn swd(&mut self) -> SWD_W<INT_CLR_SPEC> {
128        SWD_W::new(self, 15)
129    }
130    #[doc = "Bit 16 - Clears the interrupt triggered when the 32 kHz crystal is dead."]
131    #[inline(always)]
132    pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_CLR_SPEC> {
133        XTAL32K_DEAD_W::new(self, 16)
134    }
135    #[doc = "Bit 17 - Clears the interrupt triggered when the ULP-RISCV is trapped."]
136    #[inline(always)]
137    pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_CLR_SPEC> {
138        COCPU_TRAP_W::new(self, 17)
139    }
140    #[doc = "Bit 18 - Clears the interrupt triggered when touch sensor times out."]
141    #[inline(always)]
142    pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_CLR_SPEC> {
143        TOUCH_TIMEOUT_W::new(self, 18)
144    }
145    #[doc = "Bit 19 - Clears the interrupt triggered when a glitch is detected."]
146    #[inline(always)]
147    pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
148        GLITCH_DET_W::new(self, 19)
149    }
150}
151#[doc = "RTC interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct INT_CLR_SPEC;
153impl crate::RegisterSpec for INT_CLR_SPEC {
154    type Ux = u32;
155}
156#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
157impl crate::Writable for INT_CLR_SPEC {
158    type Safety = crate::Unsafe;
159    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
160    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_ffff;
161}
162#[doc = "`reset()` method sets INT_CLR to value 0"]
163impl crate::Resettable for INT_CLR_SPEC {
164    const RESET_VALUE: u32 = 0;
165}
esp32s2/rtc_cntl/int_clr.rs

esp32s2/rtc_cntl/
int_clr.rs
