1#[doc = "Register `PRO_AHB_1` reader"]
2pub type R = crate::R<PRO_AHB_1_SPEC>;
3#[doc = "Register `PRO_AHB_1` writer"]
4pub type W = crate::W<PRO_AHB_1_SPEC>;
5#[doc = "Field `PRO_AHB_RTCSLOW_0_SPLTADDR` reader - Configure the split address of RTCSlow_0 for PeriBus2 access."]
6pub type PRO_AHB_RTCSLOW_0_SPLTADDR_R = crate::FieldReader<u16>;
7#[doc = "Field `PRO_AHB_RTCSLOW_0_SPLTADDR` writer - Configure the split address of RTCSlow_0 for PeriBus2 access."]
8pub type PRO_AHB_RTCSLOW_0_SPLTADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
9#[doc = "Field `PRO_AHB_RTCSLOW_0_L_F` reader - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region."]
10pub type PRO_AHB_RTCSLOW_0_L_F_R = crate::BitReader;
11#[doc = "Field `PRO_AHB_RTCSLOW_0_L_F` writer - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region."]
12pub type PRO_AHB_RTCSLOW_0_L_F_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PRO_AHB_RTCSLOW_0_L_R` reader - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region."]
14pub type PRO_AHB_RTCSLOW_0_L_R_R = crate::BitReader;
15#[doc = "Field `PRO_AHB_RTCSLOW_0_L_R` writer - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region."]
16pub type PRO_AHB_RTCSLOW_0_L_R_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PRO_AHB_RTCSLOW_0_L_W` reader - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region."]
18pub type PRO_AHB_RTCSLOW_0_L_W_R = crate::BitReader;
19#[doc = "Field `PRO_AHB_RTCSLOW_0_L_W` writer - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region."]
20pub type PRO_AHB_RTCSLOW_0_L_W_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PRO_AHB_RTCSLOW_0_H_F` reader - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region."]
22pub type PRO_AHB_RTCSLOW_0_H_F_R = crate::BitReader;
23#[doc = "Field `PRO_AHB_RTCSLOW_0_H_F` writer - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region."]
24pub type PRO_AHB_RTCSLOW_0_H_F_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PRO_AHB_RTCSLOW_0_H_R` reader - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region."]
26pub type PRO_AHB_RTCSLOW_0_H_R_R = crate::BitReader;
27#[doc = "Field `PRO_AHB_RTCSLOW_0_H_R` writer - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region."]
28pub type PRO_AHB_RTCSLOW_0_H_R_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PRO_AHB_RTCSLOW_0_H_W` reader - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region."]
30pub type PRO_AHB_RTCSLOW_0_H_W_R = crate::BitReader;
31#[doc = "Field `PRO_AHB_RTCSLOW_0_H_W` writer - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region."]
32pub type PRO_AHB_RTCSLOW_0_H_W_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bits 0:10 - Configure the split address of RTCSlow_0 for PeriBus2 access."]
35 #[inline(always)]
36 pub fn pro_ahb_rtcslow_0_spltaddr(&self) -> PRO_AHB_RTCSLOW_0_SPLTADDR_R {
37 PRO_AHB_RTCSLOW_0_SPLTADDR_R::new((self.bits & 0x07ff) as u16)
38 }
39 #[doc = "Bit 11 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region."]
40 #[inline(always)]
41 pub fn pro_ahb_rtcslow_0_l_f(&self) -> PRO_AHB_RTCSLOW_0_L_F_R {
42 PRO_AHB_RTCSLOW_0_L_F_R::new(((self.bits >> 11) & 1) != 0)
43 }
44 #[doc = "Bit 12 - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region."]
45 #[inline(always)]
46 pub fn pro_ahb_rtcslow_0_l_r(&self) -> PRO_AHB_RTCSLOW_0_L_R_R {
47 PRO_AHB_RTCSLOW_0_L_R_R::new(((self.bits >> 12) & 1) != 0)
48 }
49 #[doc = "Bit 13 - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region."]
50 #[inline(always)]
51 pub fn pro_ahb_rtcslow_0_l_w(&self) -> PRO_AHB_RTCSLOW_0_L_W_R {
52 PRO_AHB_RTCSLOW_0_L_W_R::new(((self.bits >> 13) & 1) != 0)
53 }
54 #[doc = "Bit 14 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region."]
55 #[inline(always)]
56 pub fn pro_ahb_rtcslow_0_h_f(&self) -> PRO_AHB_RTCSLOW_0_H_F_R {
57 PRO_AHB_RTCSLOW_0_H_F_R::new(((self.bits >> 14) & 1) != 0)
58 }
59 #[doc = "Bit 15 - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region."]
60 #[inline(always)]
61 pub fn pro_ahb_rtcslow_0_h_r(&self) -> PRO_AHB_RTCSLOW_0_H_R_R {
62 PRO_AHB_RTCSLOW_0_H_R_R::new(((self.bits >> 15) & 1) != 0)
63 }
64 #[doc = "Bit 16 - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region."]
65 #[inline(always)]
66 pub fn pro_ahb_rtcslow_0_h_w(&self) -> PRO_AHB_RTCSLOW_0_H_W_R {
67 PRO_AHB_RTCSLOW_0_H_W_R::new(((self.bits >> 16) & 1) != 0)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("PRO_AHB_1")
74 .field(
75 "pro_ahb_rtcslow_0_spltaddr",
76 &self.pro_ahb_rtcslow_0_spltaddr(),
77 )
78 .field("pro_ahb_rtcslow_0_l_f", &self.pro_ahb_rtcslow_0_l_f())
79 .field("pro_ahb_rtcslow_0_l_r", &self.pro_ahb_rtcslow_0_l_r())
80 .field("pro_ahb_rtcslow_0_l_w", &self.pro_ahb_rtcslow_0_l_w())
81 .field("pro_ahb_rtcslow_0_h_f", &self.pro_ahb_rtcslow_0_h_f())
82 .field("pro_ahb_rtcslow_0_h_r", &self.pro_ahb_rtcslow_0_h_r())
83 .field("pro_ahb_rtcslow_0_h_w", &self.pro_ahb_rtcslow_0_h_w())
84 .finish()
85 }
86}
87impl W {
88 #[doc = "Bits 0:10 - Configure the split address of RTCSlow_0 for PeriBus2 access."]
89 #[inline(always)]
90 pub fn pro_ahb_rtcslow_0_spltaddr(&mut self) -> PRO_AHB_RTCSLOW_0_SPLTADDR_W<PRO_AHB_1_SPEC> {
91 PRO_AHB_RTCSLOW_0_SPLTADDR_W::new(self, 0)
92 }
93 #[doc = "Bit 11 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region."]
94 #[inline(always)]
95 pub fn pro_ahb_rtcslow_0_l_f(&mut self) -> PRO_AHB_RTCSLOW_0_L_F_W<PRO_AHB_1_SPEC> {
96 PRO_AHB_RTCSLOW_0_L_F_W::new(self, 11)
97 }
98 #[doc = "Bit 12 - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region."]
99 #[inline(always)]
100 pub fn pro_ahb_rtcslow_0_l_r(&mut self) -> PRO_AHB_RTCSLOW_0_L_R_W<PRO_AHB_1_SPEC> {
101 PRO_AHB_RTCSLOW_0_L_R_W::new(self, 12)
102 }
103 #[doc = "Bit 13 - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region."]
104 #[inline(always)]
105 pub fn pro_ahb_rtcslow_0_l_w(&mut self) -> PRO_AHB_RTCSLOW_0_L_W_W<PRO_AHB_1_SPEC> {
106 PRO_AHB_RTCSLOW_0_L_W_W::new(self, 13)
107 }
108 #[doc = "Bit 14 - Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region."]
109 #[inline(always)]
110 pub fn pro_ahb_rtcslow_0_h_f(&mut self) -> PRO_AHB_RTCSLOW_0_H_F_W<PRO_AHB_1_SPEC> {
111 PRO_AHB_RTCSLOW_0_H_F_W::new(self, 14)
112 }
113 #[doc = "Bit 15 - Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region."]
114 #[inline(always)]
115 pub fn pro_ahb_rtcslow_0_h_r(&mut self) -> PRO_AHB_RTCSLOW_0_H_R_W<PRO_AHB_1_SPEC> {
116 PRO_AHB_RTCSLOW_0_H_R_W::new(self, 15)
117 }
118 #[doc = "Bit 16 - Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region."]
119 #[inline(always)]
120 pub fn pro_ahb_rtcslow_0_h_w(&mut self) -> PRO_AHB_RTCSLOW_0_H_W_W<PRO_AHB_1_SPEC> {
121 PRO_AHB_RTCSLOW_0_H_W_W::new(self, 16)
122 }
123}
124#[doc = "PeriBus2 permission control register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_ahb_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_ahb_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
125pub struct PRO_AHB_1_SPEC;
126impl crate::RegisterSpec for PRO_AHB_1_SPEC {
127 type Ux = u32;
128}
129#[doc = "`read()` method returns [`pro_ahb_1::R`](R) reader structure"]
130impl crate::Readable for PRO_AHB_1_SPEC {}
131#[doc = "`write(|w| ..)` method takes [`pro_ahb_1::W`](W) writer structure"]
132impl crate::Writable for PRO_AHB_1_SPEC {
133 type Safety = crate::Unsafe;
134 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
135 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
136}
137#[doc = "`reset()` method sets PRO_AHB_1 to value 0x0001_f800"]
138impl crate::Resettable for PRO_AHB_1_SPEC {
139 const RESET_VALUE: u32 = 0x0001_f800;
140}