esp32s2/i2c0/
fifo_conf.rs

1#[doc = "Register `FIFO_CONF` reader"]
2pub type R = crate::R<FIFO_CONF_SPEC>;
3#[doc = "Register `FIFO_CONF` writer"]
4pub type W = crate::W<FIFO_CONF_SPEC>;
5#[doc = "Field `RXFIFO_WM_THRHD` reader - The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD\\[4:0\\], I2C_RXFIFO_WM_INT_RAW bit will be valid."]
6pub type RXFIFO_WM_THRHD_R = crate::FieldReader;
7#[doc = "Field `RXFIFO_WM_THRHD` writer - The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD\\[4:0\\], I2C_RXFIFO_WM_INT_RAW bit will be valid."]
8pub type RXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `TXFIFO_WM_THRHD` reader - The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD\\[4:0\\], I2C_TXFIFO_WM_INT_RAW bit will be valid."]
10pub type TXFIFO_WM_THRHD_R = crate::FieldReader;
11#[doc = "Field `TXFIFO_WM_THRHD` writer - The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD\\[4:0\\], I2C_TXFIFO_WM_INT_RAW bit will be valid."]
12pub type TXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `NONFIFO_EN` reader - Set this bit to enable APB non-FIFO mode."]
14pub type NONFIFO_EN_R = crate::BitReader;
15#[doc = "Field `NONFIFO_EN` writer - Set this bit to enable APB non-FIFO mode."]
16pub type NONFIFO_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FIFO_ADDR_CFG_EN` reader - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM."]
18pub type FIFO_ADDR_CFG_EN_R = crate::BitReader;
19#[doc = "Field `FIFO_ADDR_CFG_EN` writer - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM."]
20pub type FIFO_ADDR_CFG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RX_FIFO_RST` reader - Set this bit to reset RX FIFO."]
22pub type RX_FIFO_RST_R = crate::BitReader;
23#[doc = "Field `RX_FIFO_RST` writer - Set this bit to reset RX FIFO."]
24pub type RX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TX_FIFO_RST` reader - Set this bit to reset TX FIFO."]
26pub type TX_FIFO_RST_R = crate::BitReader;
27#[doc = "Field `TX_FIFO_RST` writer - Set this bit to reset TX FIFO."]
28pub type TX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `NONFIFO_RX_THRES` reader - When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data."]
30pub type NONFIFO_RX_THRES_R = crate::FieldReader;
31#[doc = "Field `NONFIFO_RX_THRES` writer - When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data."]
32pub type NONFIFO_RX_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
33#[doc = "Field `NONFIFO_TX_THRES` reader - When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data."]
34pub type NONFIFO_TX_THRES_R = crate::FieldReader;
35#[doc = "Field `NONFIFO_TX_THRES` writer - When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data."]
36pub type NONFIFO_TX_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
37#[doc = "Field `FIFO_PRT_EN` reader - The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty."]
38pub type FIFO_PRT_EN_R = crate::BitReader;
39#[doc = "Field `FIFO_PRT_EN` writer - The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty."]
40pub type FIFO_PRT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bits 0:4 - The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD\\[4:0\\], I2C_RXFIFO_WM_INT_RAW bit will be valid."]
43    #[inline(always)]
44    pub fn rxfifo_wm_thrhd(&self) -> RXFIFO_WM_THRHD_R {
45        RXFIFO_WM_THRHD_R::new((self.bits & 0x1f) as u8)
46    }
47    #[doc = "Bits 5:9 - The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD\\[4:0\\], I2C_TXFIFO_WM_INT_RAW bit will be valid."]
48    #[inline(always)]
49    pub fn txfifo_wm_thrhd(&self) -> TXFIFO_WM_THRHD_R {
50        TXFIFO_WM_THRHD_R::new(((self.bits >> 5) & 0x1f) as u8)
51    }
52    #[doc = "Bit 10 - Set this bit to enable APB non-FIFO mode."]
53    #[inline(always)]
54    pub fn nonfifo_en(&self) -> NONFIFO_EN_R {
55        NONFIFO_EN_R::new(((self.bits >> 10) & 1) != 0)
56    }
57    #[doc = "Bit 11 - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM."]
58    #[inline(always)]
59    pub fn fifo_addr_cfg_en(&self) -> FIFO_ADDR_CFG_EN_R {
60        FIFO_ADDR_CFG_EN_R::new(((self.bits >> 11) & 1) != 0)
61    }
62    #[doc = "Bit 12 - Set this bit to reset RX FIFO."]
63    #[inline(always)]
64    pub fn rx_fifo_rst(&self) -> RX_FIFO_RST_R {
65        RX_FIFO_RST_R::new(((self.bits >> 12) & 1) != 0)
66    }
67    #[doc = "Bit 13 - Set this bit to reset TX FIFO."]
68    #[inline(always)]
69    pub fn tx_fifo_rst(&self) -> TX_FIFO_RST_R {
70        TX_FIFO_RST_R::new(((self.bits >> 13) & 1) != 0)
71    }
72    #[doc = "Bits 14:19 - When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data."]
73    #[inline(always)]
74    pub fn nonfifo_rx_thres(&self) -> NONFIFO_RX_THRES_R {
75        NONFIFO_RX_THRES_R::new(((self.bits >> 14) & 0x3f) as u8)
76    }
77    #[doc = "Bits 20:25 - When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data."]
78    #[inline(always)]
79    pub fn nonfifo_tx_thres(&self) -> NONFIFO_TX_THRES_R {
80        NONFIFO_TX_THRES_R::new(((self.bits >> 20) & 0x3f) as u8)
81    }
82    #[doc = "Bit 26 - The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty."]
83    #[inline(always)]
84    pub fn fifo_prt_en(&self) -> FIFO_PRT_EN_R {
85        FIFO_PRT_EN_R::new(((self.bits >> 26) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("FIFO_CONF")
92            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
93            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
94            .field("nonfifo_en", &self.nonfifo_en())
95            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
96            .field("rx_fifo_rst", &self.rx_fifo_rst())
97            .field("tx_fifo_rst", &self.tx_fifo_rst())
98            .field("nonfifo_rx_thres", &self.nonfifo_rx_thres())
99            .field("nonfifo_tx_thres", &self.nonfifo_tx_thres())
100            .field("fifo_prt_en", &self.fifo_prt_en())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bits 0:4 - The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD\\[4:0\\], I2C_RXFIFO_WM_INT_RAW bit will be valid."]
106    #[inline(always)]
107    pub fn rxfifo_wm_thrhd(&mut self) -> RXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
108        RXFIFO_WM_THRHD_W::new(self, 0)
109    }
110    #[doc = "Bits 5:9 - The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD\\[4:0\\], I2C_TXFIFO_WM_INT_RAW bit will be valid."]
111    #[inline(always)]
112    pub fn txfifo_wm_thrhd(&mut self) -> TXFIFO_WM_THRHD_W<FIFO_CONF_SPEC> {
113        TXFIFO_WM_THRHD_W::new(self, 5)
114    }
115    #[doc = "Bit 10 - Set this bit to enable APB non-FIFO mode."]
116    #[inline(always)]
117    pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W<FIFO_CONF_SPEC> {
118        NONFIFO_EN_W::new(self, 10)
119    }
120    #[doc = "Bit 11 - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM."]
121    #[inline(always)]
122    pub fn fifo_addr_cfg_en(&mut self) -> FIFO_ADDR_CFG_EN_W<FIFO_CONF_SPEC> {
123        FIFO_ADDR_CFG_EN_W::new(self, 11)
124    }
125    #[doc = "Bit 12 - Set this bit to reset RX FIFO."]
126    #[inline(always)]
127    pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W<FIFO_CONF_SPEC> {
128        RX_FIFO_RST_W::new(self, 12)
129    }
130    #[doc = "Bit 13 - Set this bit to reset TX FIFO."]
131    #[inline(always)]
132    pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W<FIFO_CONF_SPEC> {
133        TX_FIFO_RST_W::new(self, 13)
134    }
135    #[doc = "Bits 14:19 - When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data."]
136    #[inline(always)]
137    pub fn nonfifo_rx_thres(&mut self) -> NONFIFO_RX_THRES_W<FIFO_CONF_SPEC> {
138        NONFIFO_RX_THRES_W::new(self, 14)
139    }
140    #[doc = "Bits 20:25 - When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data."]
141    #[inline(always)]
142    pub fn nonfifo_tx_thres(&mut self) -> NONFIFO_TX_THRES_W<FIFO_CONF_SPEC> {
143        NONFIFO_TX_THRES_W::new(self, 20)
144    }
145    #[doc = "Bit 26 - The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty."]
146    #[inline(always)]
147    pub fn fifo_prt_en(&mut self) -> FIFO_PRT_EN_W<FIFO_CONF_SPEC> {
148        FIFO_PRT_EN_W::new(self, 26)
149    }
150}
151#[doc = "FIFO configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct FIFO_CONF_SPEC;
153impl crate::RegisterSpec for FIFO_CONF_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`fifo_conf::R`](R) reader structure"]
157impl crate::Readable for FIFO_CONF_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`fifo_conf::W`](W) writer structure"]
159impl crate::Writable for FIFO_CONF_SPEC {
160    type Safety = crate::Unsafe;
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets FIFO_CONF to value 0x0555_408b"]
165impl crate::Resettable for FIFO_CONF_SPEC {
166    const RESET_VALUE: u32 = 0x0555_408b;
167}
esp32s2/i2c0/fifo_conf.rs

esp32s2/i2c0/
fifo_conf.rs
