Module uhci0

Universal Host Controller Interface 0

Re-exports

• pub use self::q::Q;

Modules

• ahb_test
  AHB test register
• conf0
  UHCI configuration register
• conf1
  UHCI configuration register
• date
  UHCI version control register
• dma_in_dscr
  The third word of the next receive descriptor
• dma_in_dscr_bf0
  The third word of current receive descriptor
• dma_in_err_eof_des_addr
  Inlink descriptor address when errors occur
• dma_in_link
  Link descriptor address and control
• dma_in_pop
  Pop control register of RX FIFO
• dma_in_status
  UHCI data-input status register
• dma_in_suc_eof_des_addr
  Inlink descriptor address when EOF occurs
• dma_out_dscr
  The third word of the next transmit descriptor
• dma_out_dscr_bf0
  The third word of current transmit descriptor
• dma_out_eof_bfr_des_addr
  Outlink descriptor address before the last transmit descriptor
• dma_out_eof_des_addr
  Outlink descriptor address when EOF occurs
• dma_out_link
  Link descriptor address and control
• dma_out_push
  Push control register of TX FIFO
• dma_out_status
  DMA data-output status register
• esc_conf
  Escape sequence configuration register %s
• escape_conf
  Escape character configuration
• hung_conf
  Timeout configuration
• int_clr
  Interrupt clear bits
• int_ena
  Interrupt enable bits
• int_raw
  Raw interrupt status
• int_st
  Masked interrupt status
• pkt_thres
  Configure register for packet length
• q
  Cluster Cluster Q%s, containing Q?_WORD0, Q?_WORD1
• quick_sent
  UHCI quick_sent configuration register
• rx_head
  UHCI packet header register
• state0
  UHCI decoder status register
• state1
  UHCI encoder status register

Structs

• RegisterBlock
  Register block

Type Aliases

• AHB_TEST
  AHB_TEST (rw) register accessor: AHB test register
• CONF0
  CONF0 (rw) register accessor: UHCI configuration register
• CONF1
  CONF1 (rw) register accessor: UHCI configuration register
• DATE
  DATE (rw) register accessor: UHCI version control register
• DMA_IN_DSCR
  DMA_IN_DSCR (r) register accessor: The third word of the next receive descriptor
• DMA_IN_DSCR_BF0
  DMA_IN_DSCR_BF0 (r) register accessor: The third word of current receive descriptor
• DMA_IN_ERR_EOF_DES_ADDR
  DMA_IN_ERR_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when errors occur
• DMA_IN_LINK
  DMA_IN_LINK (rw) register accessor: Link descriptor address and control
• DMA_IN_POP
  DMA_IN_POP (rw) register accessor: Pop control register of RX FIFO
• DMA_IN_STATUS
  DMA_IN_STATUS (r) register accessor: UHCI data-input status register
• DMA_IN_SUC_EOF_DES_ADDR
  DMA_IN_SUC_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when EOF occurs
• DMA_OUT_DSCR
  DMA_OUT_DSCR (r) register accessor: The third word of the next transmit descriptor
• DMA_OUT_DSCR_BF0
  DMA_OUT_DSCR_BF0 (r) register accessor: The third word of current transmit descriptor
• DMA_OUT_EOF_BFR_DES_ADDR
  DMA_OUT_EOF_BFR_DES_ADDR (r) register accessor: Outlink descriptor address before the last transmit descriptor
• DMA_OUT_EOF_DES_ADDR
  DMA_OUT_EOF_DES_ADDR (r) register accessor: Outlink descriptor address when EOF occurs
• DMA_OUT_LINK
  DMA_OUT_LINK (rw) register accessor: Link descriptor address and control
• DMA_OUT_PUSH
  DMA_OUT_PUSH (rw) register accessor: Push control register of TX FIFO
• DMA_OUT_STATUS
  DMA_OUT_STATUS (r) register accessor: DMA data-output status register
• ESCAPE_CONF
  ESCAPE_CONF (rw) register accessor: Escape character configuration
• ESC_CONF
  ESC_CONF (rw) register accessor: Escape sequence configuration register %s
• HUNG_CONF
  HUNG_CONF (rw) register accessor: Timeout configuration
• INT_CLR
  INT_CLR (w) register accessor: Interrupt clear bits
• INT_ENA
  INT_ENA (rw) register accessor: Interrupt enable bits
• INT_RAW
  INT_RAW (r) register accessor: Raw interrupt status
• INT_ST
  INT_ST (r) register accessor: Masked interrupt status
• PKT_THRES
  PKT_THRES (rw) register accessor: Configure register for packet length
• QUICK_SENT
  QUICK_SENT (rw) register accessor: UHCI quick_sent configuration register
• RX_HEAD
  RX_HEAD (r) register accessor: UHCI packet header register
• STATE0
  STATE0 (r) register accessor: UHCI decoder status register
• STATE1
  STATE1 (r) register accessor: UHCI encoder status register