Enum Interrupt

#[repr(u16)]
pub enum Interrupt {
    WIFI_MAC = 0,
    WIFI_NMI = 1,
    WIFI_PWR = 2,
    WIFI_BB = 3,
    BT_MAC = 4,
    BT_BB = 5,
    BT_BB_NMI = 6,
    RWBT = 7,
    RWBLE = 8,
    RWBT_NMI = 9,
    RWBLE_NMI = 10,
    SLC0 = 11,
    SLC1 = 12,
    UHCI0 = 13,
    UHCI1 = 14,
    TG0_T0_LEVEL = 15,
    TG0_T1_LEVEL = 16,
    TG0_WDT_LEVEL = 17,
    TG0_LACT_LEVEL = 18,
    TG1_T0_LEVEL = 19,
    TG1_T1_LEVEL = 20,
    TG1_WDT_LEVEL = 21,
    TG1_LACT_LEVEL = 22,
    GPIO = 23,
    GPIO_NMI = 24,
    GPIO_INTR_2 = 25,
    GPIO_NMI_2 = 26,
    DEDICATED_GPIO = 27,
    FROM_CPU_INTR0 = 28,
    FROM_CPU_INTR1 = 29,
    FROM_CPU_INTR2 = 30,
    FROM_CPU_INTR3 = 31,
    SPI1 = 32,
    SPI2 = 33,
    SPI3 = 34,
    I2S0 = 35,
    I2S1 = 36,
    UART0 = 37,
    UART1 = 38,
    UART2 = 39,
    SDIO_HOST = 40,
    LEDC = 45,
    EFUSE = 46,
    TWAI0 = 47,
    USB = 48,
    RTC_CORE = 49,
    RMT = 50,
    PCNT = 51,
    I2C_EXT0 = 52,
    I2C_EXT1 = 53,
    RSA = 54,
    SHA = 55,
    AES = 56,
    SPI2_DMA = 57,
    SPI3_DMA = 58,
    WDT = 59,
    TIMER1 = 60,
    TIMER2 = 61,
    TG0_T0_EDGE = 62,
    TG0_T1_EDGE = 63,
    TG0_WDT_EDGE = 64,
    TG0_LACT_EDGE = 65,
    TG1_T0_EDGE = 66,
    TG1_T1_EDGE = 67,
    TG1_WDT_EDGE = 68,
    TG1_LACT_EDGE = 69,
    CACHE_IA = 70,
    SYSTIMER_TARGET0 = 71,
    SYSTIMER_TARGET1 = 72,
    SYSTIMER_TARGET2 = 73,
    PMS_PRO_IRAM0_ILG = 75,
    PMS_PRO_DRAM0_ILG = 76,
    PMS_PRO_DPORT_ILG = 77,
    PMS_PRO_AHB_ILG = 78,
    PMS_PRO_CACHE_ILG = 79,
    PMS_DMA_APB_I_ILG = 80,
    PMS_DMA_RX_I_ILG = 81,
    PMS_DMA_TX_I_ILG = 82,
    SPI0_REJECT_CACHE = 83,
    SPI4_DMA = 85,
    SPI4 = 86,
    ICACHE_PRELOAD = 87,
    DCACHE_PRELOAD = 88,
    APB_ADC = 89,
    CPU_PERI_ERR = 91,
    APB_PERI_ERR = 92,
    DCACHE_SYNC = 93,
    ICACHE_SYNC = 94,
}

Enumeration of all the interrupts.

Variants

WIFI_MAC = 0

0 - WIFI_MAC

WIFI_NMI = 1

1 - WIFI_NMI

WIFI_PWR = 2

2 - WIFI_PWR

WIFI_BB = 3

3 - WIFI_BB

BT_MAC = 4

4 - BT_MAC

BT_BB = 5

5 - BT_BB

BT_BB_NMI = 6

6 - BT_BB_NMI

RWBT = 7

7 - RWBT

RWBLE = 8

8 - RWBLE

RWBT_NMI = 9

9 - RWBT_NMI

RWBLE_NMI = 10

10 - RWBLE_NMI

SLC0 = 11

11 - SLC0

SLC1 = 12

12 - SLC1

UHCI0 = 13

13 - UHCI0

UHCI1 = 14

14 - UHCI1

TG0_T0_LEVEL = 15

15 - TG0_T0_LEVEL

TG0_T1_LEVEL = 16

16 - TG0_T1_LEVEL

TG0_WDT_LEVEL = 17

17 - TG0_WDT_LEVEL

TG0_LACT_LEVEL = 18

18 - TG0_LACT_LEVEL

TG1_T0_LEVEL = 19

19 - TG1_T0_LEVEL

TG1_T1_LEVEL = 20

20 - TG1_T1_LEVEL

TG1_WDT_LEVEL = 21

21 - TG1_WDT_LEVEL

TG1_LACT_LEVEL = 22

22 - TG1_LACT_LEVEL

GPIO = 23

23 - GPIO

GPIO_NMI = 24

24 - GPIO_NMI

GPIO_INTR_2 = 25

25 - GPIO_INTR_2

GPIO_NMI_2 = 26

26 - GPIO_NMI_2

DEDICATED_GPIO = 27

27 - DEDICATED_GPIO

FROM_CPU_INTR0 = 28

28 - FROM_CPU_INTR0

FROM_CPU_INTR1 = 29

29 - FROM_CPU_INTR1

FROM_CPU_INTR2 = 30

30 - FROM_CPU_INTR2

FROM_CPU_INTR3 = 31

31 - FROM_CPU_INTR3

SPI1 = 32

32 - SPI1

SPI2 = 33

33 - SPI2

SPI3 = 34

34 - SPI3

I2S0 = 35

35 - I2S0

I2S1 = 36

36 - I2S1

UART0 = 37

37 - UART0

UART1 = 38

38 - UART1

UART2 = 39

39 - UART2

SDIO_HOST = 40

40 - SDIO_HOST

LEDC = 45

45 - LEDC

EFUSE = 46

46 - EFUSE

TWAI0 = 47

47 - TWAI0

USB = 48

48 - USB

RTC_CORE = 49

49 - RTC_CORE

RMT = 50

50 - RMT

PCNT = 51

51 - PCNT

I2C_EXT0 = 52

52 - I2C_EXT0

I2C_EXT1 = 53

53 - I2C_EXT1

RSA = 54

54 - RSA

SHA = 55

55 - SHA

AES = 56

56 - AES

SPI2_DMA = 57

57 - SPI2_DMA

SPI3_DMA = 58

58 - SPI3_DMA

WDT = 59

59 - WDT

TIMER1 = 60

60 - TIMER1

TIMER2 = 61

61 - TIMER2

TG0_T0_EDGE = 62

62 - TG0_T0_EDGE

TG0_T1_EDGE = 63

63 - TG0_T1_EDGE

TG0_WDT_EDGE = 64

64 - TG0_WDT_EDGE

TG0_LACT_EDGE = 65

65 - TG0_LACT_EDGE

TG1_T0_EDGE = 66

66 - TG1_T0_EDGE

TG1_T1_EDGE = 67

67 - TG1_T1_EDGE

TG1_WDT_EDGE = 68

68 - TG1_WDT_EDGE

TG1_LACT_EDGE = 69

69 - TG1_LACT_EDGE

CACHE_IA = 70

70 - CACHE_IA

SYSTIMER_TARGET0 = 71

71 - SYSTIMER_TARGET0

SYSTIMER_TARGET1 = 72

72 - SYSTIMER_TARGET1

SYSTIMER_TARGET2 = 73

73 - SYSTIMER_TARGET2

PMS_PRO_IRAM0_ILG = 75

75 - PMS_PRO_IRAM0_ILG

PMS_PRO_DRAM0_ILG = 76

76 - PMS_PRO_DRAM0_ILG

PMS_PRO_DPORT_ILG = 77

77 - PMS_PRO_DPORT_ILG

PMS_PRO_AHB_ILG = 78

78 - PMS_PRO_AHB_ILG

PMS_PRO_CACHE_ILG = 79

79 - PMS_PRO_CACHE_ILG

PMS_DMA_APB_I_ILG = 80

80 - PMS_DMA_APB_I_ILG

PMS_DMA_RX_I_ILG = 81

81 - PMS_DMA_RX_I_ILG

PMS_DMA_TX_I_ILG = 82

82 - PMS_DMA_TX_I_ILG

SPI0_REJECT_CACHE = 83

83 - SPI0_REJECT_CACHE

SPI4_DMA = 85

85 - SPI4_DMA

SPI4 = 86

86 - SPI4

ICACHE_PRELOAD = 87

87 - ICACHE_PRELOAD

DCACHE_PRELOAD = 88

88 - DCACHE_PRELOAD

APB_ADC = 89

89 - APB_ADC

CPU_PERI_ERR = 91

91 - CPU_PERI_ERR

APB_PERI_ERR = 92

92 - APB_PERI_ERR

DCACHE_SYNC = 93

93 - DCACHE_SYNC

ICACHE_SYNC = 94

94 - ICACHE_SYNC

Implementations

impl Interrupt

pub fn try_from(value: u16) -> Result<Self, TryFromInterruptError>

Attempt to convert a given value into an Interrupt

Trait Implementations

impl Clone for Interrupt

fn clone(&self) -> Interrupt

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Interrupt

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Interrupt

fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Interrupt

impl Eq for Interrupt

impl StructuralPartialEq for Interrupt