Type Alias esp32s2::spi0::hold::R

pub type R = R<HOLD_SPEC>;

Register HOLD reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn int_hold_ena(&self) -> INT_HOLD_ENA_R

Bits 0:1 - This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state.

pub fn val(&self) -> VAL_R

Bit 2 - spi hold output value, which should be used with SPI_HOLD_OUT_EN. Can be configured in CONF state.

pub fn out_en(&self) -> OUT_EN_R

Bit 3 - Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with SPI_EXT_HOLD_EN and other usr hold signals. Can be configured in CONF state.

pub fn out_time(&self) -> OUT_TIME_R

Bits 4:6 - set the hold cycles of output spi_hold signal when SPI_HOLD_OUT_EN is enable. Can be configured in CONF state.

pub fn dma_seg_trans_done(&self) -> DMA_SEG_TRANS_DONE_R

Bit 7 - 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.