Type Alias esp32s2::apb_saradc::ctrl::W

pub type W = W<CTRL_SPEC>;

Register CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn start_force(&mut self) -> START_FORCE_W<'_, CTRL_SPEC>

Bit 0 - 0: select FSM to start SAR ADC. 1: select software to start SAR ADC.

pub fn start(&mut self) -> START_W<'_, CTRL_SPEC>

Bit 1 - Start SAR ADC by software.

pub fn work_mode(&mut self) -> WORK_MODE_W<'_, CTRL_SPEC>

Bits 3:4 - 0: single-channel scan mode. 1: double-channel scan mode. 2: alternate-channel scan mode.

pub fn sar_sel(&mut self) -> SAR_SEL_W<'_, CTRL_SPEC>

Bit 5 - 0: select SAR ADC1. 1: select SAR ADC2, only work for single-channel scan mode.

pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W<'_, CTRL_SPEC>

Bit 6 - SAR clock gate enable bit.

pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W<'_, CTRL_SPEC>

Bits 7:14 - SAR clock divider

pub fn sar1_patt_len(&mut self) -> SAR1_PATT_LEN_W<'_, CTRL_SPEC>

Bits 15:18 - 0 ~ 15 means length 1 ~ 16

pub fn sar2_patt_len(&mut self) -> SAR2_PATT_LEN_W<'_, CTRL_SPEC>

Bits 19:22 - 0 ~ 15 means length 1 ~ 16

pub fn sar1_patt_p_clear(&mut self) -> SAR1_PATT_P_CLEAR_W<'_, CTRL_SPEC>

Bit 23 - Clear the pointer of pattern table for DIG ADC1 CTRL.

pub fn sar2_patt_p_clear(&mut self) -> SAR2_PATT_P_CLEAR_W<'_, CTRL_SPEC>

Bit 24 - Clear the pointer of pattern table for DIG ADC2 CTRL.

pub fn data_sar_sel(&mut self) -> DATA_SAR_SEL_W<'_, CTRL_SPEC>

Bit 25 - 1: sar_sel will be coded to the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.

pub fn data_to_i2s(&mut self) -> DATA_TO_I2S_W<'_, CTRL_SPEC>

Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix

pub fn xpd_sar_force(&mut self) -> XPD_SAR_FORCE_W<'_, CTRL_SPEC>

Bits 27:28 - Force option to xpd sar blocks.

pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W<'_, CTRL_SPEC>

Bits 30:31 - Wait arbit signal stable after sar_done.