Type Alias esp32s2::uhci0::int_raw::R

pub type R = R<INT_RAW_SPEC>;

Register INT_RAW reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn rx_start(&self) -> RX_START_R

Bit 0 - This is the interrupt raw bit for UHCI_RX_START_INT interrupt. The interrupt is triggered when a separator has been sent.

pub fn tx_start(&self) -> TX_START_R

Bit 1 - This is the interrupt raw bit for UHCI_TX_START_INT interrupt. The interrupt is triggered when DMA detects a separator.

pub fn rx_hung(&self) -> RX_HUNG_R

Bit 2 - This is the interrupt raw bit for UHCI_RX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to receive data than the configure value.

pub fn tx_hung(&self) -> TX_HUNG_R

Bit 3 - This is the interrupt raw bit for UHCI_TX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to read data from RAM than the configured value.

pub fn in_done(&self) -> IN_DONE_R

Bit 4 - This is the interrupt raw bit for UHCI_IN_DONE_INT interrupt. The interrupt is triggered when an receive descriptor is completed.

pub fn in_suc_eof(&self) -> IN_SUC_EOF_R

Bit 5 - This is the interrupt raw bit for UHCI_IN_SUC_EOF_INT interrupt. The interrupt is triggered when a data packet has been received successfully.

pub fn in_err_eof(&self) -> IN_ERR_EOF_R

Bit 6 - This is the interrupt raw bit for UHCI_IN_ERR_EOF_INT interrupt. The interrupt is triggered when there are some errors in EOF in the receive descriptor.

pub fn out_done(&self) -> OUT_DONE_R

Bit 7 - This is the interrupt raw bit for UHCI_OUT_DONE_INT interrupt. The interrupt is triggered when an transmit descriptor is completed.

pub fn out_eof(&self) -> OUT_EOF_R

Bit 8 - This is the interrupt raw bit for UHCI_OUT_EOF_INT interrupt. The interrupt is triggered when the current descriptor’s EOF bit is 1.

pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R

Bit 9 - This is the interrupt raw bit for UHCI_IN_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the receive descriptor.

pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R

Bit 10 - This is the interrupt raw bit for UHCI_OUT_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the transmit descriptor.

pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R

Bit 11 - This is the interrupt raw bit for UHCI_IN_DSCR_EMPTY_INT interrupt. The interrupt is triggered when there are not enough inlinks for DMA.

pub fn outlink_eof_err(&self) -> OUTLINK_EOF_ERR_R

Bit 12 - This is the interrupt raw bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. The interrupt is triggered when there are some errors in EOF in the transmit descriptor.

pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R

Bit 13 - This is the interrupt raw bit for UHCI_OUT_TOTAL_EOF_INT interrupt. The interrupt is triggered when all data in the last buffer address has been sent out.

pub fn send_s_reg_q(&self) -> SEND_S_REG_Q_R

Bit 14 - This is the interrupt raw bit for UHCI_SEND_S_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using single_send mode.

pub fn send_a_reg_q(&self) -> SEND_A_REG_Q_R

Bit 15 - This is the interrupt raw bit for UHCI_SEND_A_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using always_send mode.

pub fn dma_infifo_full_wm(&self) -> DMA_INFIFO_FULL_WM_R

Bit 16 - This is the interrupt raw bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. The interrupt is triggered when the number of data bytes in DMA RX FIFO has reached the configured threshold value.