Expand description
Clock output configuration register
Structs§
- Clock output configuration register
Type Aliases§
- Field
PAD_POWER_CTRLreader - Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V. - Field
PAD_POWER_CTRLwriter - Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V. - Field
PIN_CLK_OUT1reader - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled. - Field
PIN_CLK_OUT1writer - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled. - Field
PIN_CLK_OUT2reader - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled. - Field
PIN_CLK_OUT2writer - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled. - Field
PIN_CLK_OUT3reader - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled. - Field
PIN_CLK_OUT3writer - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled. - Register
PIN_CTRLreader - Field
SWITCH_PRT_NUMreader - IO pin power switch delay, delay unit is one APB clock. - Field
SWITCH_PRT_NUMwriter - IO pin power switch delay, delay unit is one APB clock. - Register
PIN_CTRLwriter