Expand description
I2S (Inter-IC Sound) Controller 0
Modules§
- I2S module clock configuration register
- I2S configuration register
- I2S configuration register 1
- I2S configuration register 2
- I2S channel configuration register
- Constant single channel data
- Version control register
- I2S FIFO configuration register
- Address of inlink descriptor that produces EOF
- I2S DMA RX configuration register
- APB in FIFO mode register
- Address of current inlink descriptor
- Address of next inlink descriptor
- Address of next inlink data buffer
- Interrupt clear bits
- Interrupt enable bits
- Raw interrupt status
- Masked interrupt status
- I2S DMA configuration register
- I2S Hung configuration register
- I2S DMA TX status
- I2S DMA RX status
- Address of buffer relative to the outlink descriptor that produces EOF
- Address of outlink descriptor that produces EOF
- I2S DMA TX configuration register
- APB out FIFO mode register
- Address of current outlink descriptor
- Address of next outlink descriptor
- Address of next outlink data buffer
- I2S power-down configuration register
- I2S DMA RX EOF data length
- I2S sample rate register
- I2S TX status register
- I2S timing register
Structs§
- Register block
Type Aliases§
- CLKM_CONF (rw) register accessor: I2S module clock configuration register
- CONF (rw) register accessor: I2S configuration register
- CONF1 (rw) register accessor: I2S configuration register 1
- CONF2 (rw) register accessor: I2S configuration register 2
- CONF_CHAN (rw) register accessor: I2S channel configuration register
- CONF_SIGLE_DATA (rw) register accessor: Constant single channel data
- DATE (rw) register accessor: Version control register
- FIFO_CONF (rw) register accessor: I2S FIFO configuration register
- INFIFO_POP (rw) register accessor: APB in FIFO mode register
- INLINK_DSCR (r) register accessor: Address of current inlink descriptor
- INLINK_DSCR_BF0 (r) register accessor: Address of next inlink descriptor
- INLINK_DSCR_BF1 (r) register accessor: Address of next inlink data buffer
- INT_CLR (w) register accessor: Interrupt clear bits
- INT_ENA (rw) register accessor: Interrupt enable bits
- INT_RAW (r) register accessor: Raw interrupt status
- INT_ST (r) register accessor: Masked interrupt status
- IN_EOF_DES_ADDR (r) register accessor: Address of inlink descriptor that produces EOF
- IN_LINK (rw) register accessor: I2S DMA RX configuration register
- LC_CONF (rw) register accessor: I2S DMA configuration register
- LC_HUNG_CONF (rw) register accessor: I2S Hung configuration register
- LC_STATE0 (r) register accessor: I2S DMA TX status
- LC_STATE1 (r) register accessor: I2S DMA RX status
- OUTFIFO_PUSH (rw) register accessor: APB out FIFO mode register
- OUTLINK_DSCR (r) register accessor: Address of current outlink descriptor
- OUTLINK_DSCR_BF0 (r) register accessor: Address of next outlink descriptor
- OUTLINK_DSCR_BF1 (r) register accessor: Address of next outlink data buffer
- OUT_EOF_BFR_DES_ADDR (r) register accessor: Address of buffer relative to the outlink descriptor that produces EOF
- OUT_EOF_DES_ADDR (r) register accessor: Address of outlink descriptor that produces EOF
- OUT_LINK (rw) register accessor: I2S DMA TX configuration register
- PD_CONF (rw) register accessor: I2S power-down configuration register
- RXEOF_NUM (rw) register accessor: I2S DMA RX EOF data length
- SAMPLE_RATE_CONF (rw) register accessor: I2S sample rate register
- STATE (r) register accessor: I2S TX status register
- TIMING (rw) register accessor: I2S timing register