Module esp32s2::i2s0::timing

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I2S timing register

Structs§

Type Aliases§

  • DATA_ENABLE_DELAY_R
    Field DATA_ENABLE_DELAY reader - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • DATA_ENABLE_DELAY_W
    Field DATA_ENABLE_DELAY writer - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • R
    Register TIMING reader
  • RX_BCK_IN_DELAY_R
    Field RX_BCK_IN_DELAY reader - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • RX_BCK_IN_DELAY_W
    Field RX_BCK_IN_DELAY writer - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • RX_BCK_OUT_DELAY_R
    Field RX_BCK_OUT_DELAY reader - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • RX_BCK_OUT_DELAY_W
    Field RX_BCK_OUT_DELAY writer - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • RX_DSYNC_SW_R
    Field RX_DSYNC_SW reader - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge.
  • RX_DSYNC_SW_W
    Field RX_DSYNC_SW writer - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge.
  • RX_SD_IN_DELAY_R
    Field RX_SD_IN_DELAY reader - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • RX_SD_IN_DELAY_W
    Field RX_SD_IN_DELAY writer - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • RX_WS_IN_DELAY_R
    Field RX_WS_IN_DELAY reader - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • RX_WS_IN_DELAY_W
    Field RX_WS_IN_DELAY writer - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • RX_WS_OUT_DELAY_R
    Field RX_WS_OUT_DELAY reader - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • RX_WS_OUT_DELAY_W
    Field RX_WS_OUT_DELAY writer - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • TX_BCK_IN_DELAY_R
    Field TX_BCK_IN_DELAY reader - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • TX_BCK_IN_DELAY_W
    Field TX_BCK_IN_DELAY writer - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • TX_BCK_IN_INV_R
    Field TX_BCK_IN_INV reader - Set this bit to invert BCK signal input to the slave transmitter.
  • TX_BCK_IN_INV_W
    Field TX_BCK_IN_INV writer - Set this bit to invert BCK signal input to the slave transmitter.
  • TX_BCK_OUT_DELAY_R
    Field TX_BCK_OUT_DELAY reader - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • TX_BCK_OUT_DELAY_W
    Field TX_BCK_OUT_DELAY writer - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • TX_DSYNC_SW_R
    Field TX_DSYNC_SW reader - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge.
  • TX_DSYNC_SW_W
    Field TX_DSYNC_SW writer - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge.
  • TX_SD_OUT_DELAY_R
    Field TX_SD_OUT_DELAY reader - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • TX_SD_OUT_DELAY_W
    Field TX_SD_OUT_DELAY writer - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • TX_WS_IN_DELAY_R
    Field TX_WS_IN_DELAY reader - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • TX_WS_IN_DELAY_W
    Field TX_WS_IN_DELAY writer - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.
  • TX_WS_OUT_DELAY_R
    Field TX_WS_OUT_DELAY reader - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • TX_WS_OUT_DELAY_W
    Field TX_WS_OUT_DELAY writer - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.
  • W
    Register TIMING writer