Type Alias esp32s2::uhci0::conf1::R

pub type R = R<CONF1_SPEC>;

Register CONF1 reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn check_sum_en(&self) -> CHECK_SUM_EN_R

Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet.

pub fn check_seq_en(&self) -> CHECK_SEQ_EN_R

Bit 1 - This is the enable bit to check sequence number when UHCI receives a data packet.

pub fn crc_disable(&self) -> CRC_DISABLE_R

Bit 2 - Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1.

pub fn save_head(&self) -> SAVE_HEAD_R

Bit 3 - Set this bit to save the packet header when UHCI receives a data packet.

pub fn tx_check_sum_re(&self) -> TX_CHECK_SUM_RE_R

Bit 4 - Set this bit to encode the data packet with a checksum.

pub fn tx_ack_num_re(&self) -> TX_ACK_NUM_RE_R

Bit 5 - Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit.

pub fn check_owner(&self) -> CHECK_OWNER_R

Bit 6 - 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor.

pub fn wait_sw_start(&self) -> WAIT_SW_START_R

Bit 7 - The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1.

pub fn sw_start(&self) -> SW_START_R

Bit 8 - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1.

pub fn dma_infifo_full_thrs(&self) -> DMA_INFIFO_FULL_THRS_R

Bits 9:20 - This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register.