Struct esp32s2::gpio::pin::R

pub struct R(_);

Register PIN%s reader

Implementations

impl R

pub fn pin_sync2_bypass(&self) -> PIN_SYNC2_BYPASS_R

Bits 0:1 - For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.

pub fn pin_pad_driver(&self) -> PIN_PAD_DRIVER_R

Bit 2 - Pad driver selection. 0: normal output; 1: open drain output..

pub fn pin_sync1_bypass(&self) -> PIN_SYNC1_BYPASS_R

Bits 3:4 - For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.

pub fn pin_int_type(&self) -> PIN_INT_TYPE_R

Bits 7:9 - Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)

pub fn pin_wakeup_enable(&self) -> PIN_WAKEUP_ENABLE_R

Bit 10 - GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.

pub fn pin_config(&self) -> PIN_CONFIG_R

Bits 11:12 - Reserved

pub fn pin_int_ena(&self) -> PIN_INT_ENA_R

Bits 13:17 - Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled.

Methods from Deref<Target = R<PIN_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<PIN_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<PIN_SPEC>> for R

fn from(reader: R<PIN_SPEC>) -> Self

Converts to this type from the input type.