1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294

#[doc = "Register `DMA_TX_I_1` reader"]
pub type R = crate::R<DMA_TX_I_1_SPEC>;
#[doc = "Register `DMA_TX_I_1` writer"]
pub type W = crate::W<DMA_TX_I_1_SPEC>;
#[doc = "Field `DMA_TX_I_SRAM_0_R` reader - Setting to 1 grants TX Copy DMA permission to read SRAM Block 0."]
pub type DMA_TX_I_SRAM_0_R_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_0_R` writer - Setting to 1 grants TX Copy DMA permission to read SRAM Block 0."]
pub type DMA_TX_I_SRAM_0_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_0_W` reader - Setting to 1 grants TX Copy DMA permission to write SRAM Block 0."]
pub type DMA_TX_I_SRAM_0_W_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_0_W` writer - Setting to 1 grants TX Copy DMA permission to write SRAM Block 0."]
pub type DMA_TX_I_SRAM_0_W_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_1_R` reader - Setting to 1 grants TX Copy DMA permission to read SRAM Block 1."]
pub type DMA_TX_I_SRAM_1_R_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_1_R` writer - Setting to 1 grants TX Copy DMA permission to read SRAM Block 1."]
pub type DMA_TX_I_SRAM_1_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_1_W` reader - Setting to 1 grants TX Copy DMA permission to write SRAM Block 1."]
pub type DMA_TX_I_SRAM_1_W_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_1_W` writer - Setting to 1 grants TX Copy DMA permission to write SRAM Block 1."]
pub type DMA_TX_I_SRAM_1_W_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_2_R` reader - Setting to 1 grants TX Copy DMA permission to read SRAM Block 2."]
pub type DMA_TX_I_SRAM_2_R_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_2_R` writer - Setting to 1 grants TX Copy DMA permission to read SRAM Block 2."]
pub type DMA_TX_I_SRAM_2_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_2_W` reader - Setting to 1 grants TX Copy DMA permission to write SRAM Block 2."]
pub type DMA_TX_I_SRAM_2_W_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_2_W` writer - Setting to 1 grants TX Copy DMA permission to write SRAM Block 2."]
pub type DMA_TX_I_SRAM_2_W_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_3_R` reader - Setting to 1 grants TX Copy DMA permission to read SRAM Block 3."]
pub type DMA_TX_I_SRAM_3_R_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_3_R` writer - Setting to 1 grants TX Copy DMA permission to read SRAM Block 3."]
pub type DMA_TX_I_SRAM_3_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_3_W` reader - Setting to 1 grants TX Copy DMA permission to write SRAM Block 3."]
pub type DMA_TX_I_SRAM_3_W_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_3_W` writer - Setting to 1 grants TX Copy DMA permission to write SRAM Block 3."]
pub type DMA_TX_I_SRAM_3_W_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_4_SPLTADDR` reader - Configure the split address of SRAM Block 4-21 for TX Copy DMA access."]
pub type DMA_TX_I_SRAM_4_SPLTADDR_R = crate::FieldReader<u32>;
#[doc = "Field `DMA_TX_I_SRAM_4_SPLTADDR` writer - Configure the split address of SRAM Block 4-21 for TX Copy DMA access."]
pub type DMA_TX_I_SRAM_4_SPLTADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
#[doc = "Field `DMA_TX_I_SRAM_4_L_R` reader - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region."]
pub type DMA_TX_I_SRAM_4_L_R_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_4_L_R` writer - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region."]
pub type DMA_TX_I_SRAM_4_L_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_4_L_W` reader - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region."]
pub type DMA_TX_I_SRAM_4_L_W_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_4_L_W` writer - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region."]
pub type DMA_TX_I_SRAM_4_L_W_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_4_H_R` reader - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region."]
pub type DMA_TX_I_SRAM_4_H_R_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_4_H_R` writer - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region."]
pub type DMA_TX_I_SRAM_4_H_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA_TX_I_SRAM_4_H_W` reader - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region."]
pub type DMA_TX_I_SRAM_4_H_W_R = crate::BitReader;
#[doc = "Field `DMA_TX_I_SRAM_4_H_W` writer - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region."]
pub type DMA_TX_I_SRAM_4_H_W_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 0."]
    #[inline(always)]
    pub fn dma_tx_i_sram_0_r(&self) -> DMA_TX_I_SRAM_0_R_R {
        DMA_TX_I_SRAM_0_R_R::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 0."]
    #[inline(always)]
    pub fn dma_tx_i_sram_0_w(&self) -> DMA_TX_I_SRAM_0_W_R {
        DMA_TX_I_SRAM_0_W_R::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 1."]
    #[inline(always)]
    pub fn dma_tx_i_sram_1_r(&self) -> DMA_TX_I_SRAM_1_R_R {
        DMA_TX_I_SRAM_1_R_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 1."]
    #[inline(always)]
    pub fn dma_tx_i_sram_1_w(&self) -> DMA_TX_I_SRAM_1_W_R {
        DMA_TX_I_SRAM_1_W_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 2."]
    #[inline(always)]
    pub fn dma_tx_i_sram_2_r(&self) -> DMA_TX_I_SRAM_2_R_R {
        DMA_TX_I_SRAM_2_R_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 2."]
    #[inline(always)]
    pub fn dma_tx_i_sram_2_w(&self) -> DMA_TX_I_SRAM_2_W_R {
        DMA_TX_I_SRAM_2_W_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 3."]
    #[inline(always)]
    pub fn dma_tx_i_sram_3_r(&self) -> DMA_TX_I_SRAM_3_R_R {
        DMA_TX_I_SRAM_3_R_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 3."]
    #[inline(always)]
    pub fn dma_tx_i_sram_3_w(&self) -> DMA_TX_I_SRAM_3_W_R {
        DMA_TX_I_SRAM_3_W_R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bits 8:24 - Configure the split address of SRAM Block 4-21 for TX Copy DMA access."]
    #[inline(always)]
    pub fn dma_tx_i_sram_4_spltaddr(&self) -> DMA_TX_I_SRAM_4_SPLTADDR_R {
        DMA_TX_I_SRAM_4_SPLTADDR_R::new((self.bits >> 8) & 0x0001_ffff)
    }
    #[doc = "Bit 25 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region."]
    #[inline(always)]
    pub fn dma_tx_i_sram_4_l_r(&self) -> DMA_TX_I_SRAM_4_L_R_R {
        DMA_TX_I_SRAM_4_L_R_R::new(((self.bits >> 25) & 1) != 0)
    }
    #[doc = "Bit 26 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region."]
    #[inline(always)]
    pub fn dma_tx_i_sram_4_l_w(&self) -> DMA_TX_I_SRAM_4_L_W_R {
        DMA_TX_I_SRAM_4_L_W_R::new(((self.bits >> 26) & 1) != 0)
    }
    #[doc = "Bit 27 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region."]
    #[inline(always)]
    pub fn dma_tx_i_sram_4_h_r(&self) -> DMA_TX_I_SRAM_4_H_R_R {
        DMA_TX_I_SRAM_4_H_R_R::new(((self.bits >> 27) & 1) != 0)
    }
    #[doc = "Bit 28 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region."]
    #[inline(always)]
    pub fn dma_tx_i_sram_4_h_w(&self) -> DMA_TX_I_SRAM_4_H_W_R {
        DMA_TX_I_SRAM_4_H_W_R::new(((self.bits >> 28) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMA_TX_I_1")
            .field(
                "dma_tx_i_sram_0_r",
                &format_args!("{}", self.dma_tx_i_sram_0_r().bit()),
            )
            .field(
                "dma_tx_i_sram_0_w",
                &format_args!("{}", self.dma_tx_i_sram_0_w().bit()),
            )
            .field(
                "dma_tx_i_sram_1_r",
                &format_args!("{}", self.dma_tx_i_sram_1_r().bit()),
            )
            .field(
                "dma_tx_i_sram_1_w",
                &format_args!("{}", self.dma_tx_i_sram_1_w().bit()),
            )
            .field(
                "dma_tx_i_sram_2_r",
                &format_args!("{}", self.dma_tx_i_sram_2_r().bit()),
            )
            .field(
                "dma_tx_i_sram_2_w",
                &format_args!("{}", self.dma_tx_i_sram_2_w().bit()),
            )
            .field(
                "dma_tx_i_sram_3_r",
                &format_args!("{}", self.dma_tx_i_sram_3_r().bit()),
            )
            .field(
                "dma_tx_i_sram_3_w",
                &format_args!("{}", self.dma_tx_i_sram_3_w().bit()),
            )
            .field(
                "dma_tx_i_sram_4_spltaddr",
                &format_args!("{}", self.dma_tx_i_sram_4_spltaddr().bits()),
            )
            .field(
                "dma_tx_i_sram_4_l_r",
                &format_args!("{}", self.dma_tx_i_sram_4_l_r().bit()),
            )
            .field(
                "dma_tx_i_sram_4_l_w",
                &format_args!("{}", self.dma_tx_i_sram_4_l_w().bit()),
            )
            .field(
                "dma_tx_i_sram_4_h_r",
                &format_args!("{}", self.dma_tx_i_sram_4_h_r().bit()),
            )
            .field(
                "dma_tx_i_sram_4_h_w",
                &format_args!("{}", self.dma_tx_i_sram_4_h_w().bit()),
            )
            .finish()
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<DMA_TX_I_1_SPEC> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        core::fmt::Debug::fmt(&self.read(), f)
    }
}
impl W {
    #[doc = "Bit 0 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 0."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_0_r(&mut self) -> DMA_TX_I_SRAM_0_R_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_0_R_W::new(self, 0)
    }
    #[doc = "Bit 1 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 0."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_0_w(&mut self) -> DMA_TX_I_SRAM_0_W_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_0_W_W::new(self, 1)
    }
    #[doc = "Bit 2 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 1."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_1_r(&mut self) -> DMA_TX_I_SRAM_1_R_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_1_R_W::new(self, 2)
    }
    #[doc = "Bit 3 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 1."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_1_w(&mut self) -> DMA_TX_I_SRAM_1_W_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_1_W_W::new(self, 3)
    }
    #[doc = "Bit 4 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 2."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_2_r(&mut self) -> DMA_TX_I_SRAM_2_R_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_2_R_W::new(self, 4)
    }
    #[doc = "Bit 5 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 2."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_2_w(&mut self) -> DMA_TX_I_SRAM_2_W_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_2_W_W::new(self, 5)
    }
    #[doc = "Bit 6 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 3."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_3_r(&mut self) -> DMA_TX_I_SRAM_3_R_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_3_R_W::new(self, 6)
    }
    #[doc = "Bit 7 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 3."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_3_w(&mut self) -> DMA_TX_I_SRAM_3_W_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_3_W_W::new(self, 7)
    }
    #[doc = "Bits 8:24 - Configure the split address of SRAM Block 4-21 for TX Copy DMA access."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_4_spltaddr(&mut self) -> DMA_TX_I_SRAM_4_SPLTADDR_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_4_SPLTADDR_W::new(self, 8)
    }
    #[doc = "Bit 25 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_4_l_r(&mut self) -> DMA_TX_I_SRAM_4_L_R_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_4_L_R_W::new(self, 25)
    }
    #[doc = "Bit 26 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_4_l_w(&mut self) -> DMA_TX_I_SRAM_4_L_W_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_4_L_W_W::new(self, 26)
    }
    #[doc = "Bit 27 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_4_h_r(&mut self) -> DMA_TX_I_SRAM_4_H_R_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_4_H_R_W::new(self, 27)
    }
    #[doc = "Bit 28 - Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region."]
    #[inline(always)]
    #[must_use]
    pub fn dma_tx_i_sram_4_h_w(&mut self) -> DMA_TX_I_SRAM_4_H_W_W<DMA_TX_I_1_SPEC> {
        DMA_TX_I_SRAM_4_H_W_W::new(self, 28)
    }
    #[doc = r" Writes raw bits to the register."]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
}
#[doc = "TX Copy DMA permission control register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_tx_i_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_tx_i_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMA_TX_I_1_SPEC;
impl crate::RegisterSpec for DMA_TX_I_1_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`dma_tx_i_1::R`](R) reader structure"]
impl crate::Readable for DMA_TX_I_1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`dma_tx_i_1::W`](W) writer structure"]
impl crate::Writable for DMA_TX_I_1_SPEC {
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMA_TX_I_1 to value 0x1e00_00ff"]
impl crate::Resettable for DMA_TX_I_1_SPEC {
    const RESET_VALUE: Self::Ux = 0x1e00_00ff;
}