Type Alias esp32s2::extmem::cache_sync_int_ctrl::W

pub type W = W<CACHE_SYNC_INT_CTRL_SPEC>;

Register CACHE_SYNC_INT_CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn pro_icache_sync_int_ena( &mut self ) -> PRO_ICACHE_SYNC_INT_ENA_W<'_, CACHE_SYNC_INT_CTRL_SPEC>

Bit 1 - The bit is used to enable the interrupt by icache sync done.

pub fn pro_icache_sync_int_clr( &mut self ) -> PRO_ICACHE_SYNC_INT_CLR_W<'_, CACHE_SYNC_INT_CTRL_SPEC>

Bit 2 - The bit is used to clear the interrupt by icache sync done.

pub fn pro_dcache_sync_int_ena( &mut self ) -> PRO_DCACHE_SYNC_INT_ENA_W<'_, CACHE_SYNC_INT_CTRL_SPEC>

Bit 4 - The bit is used to enable the interrupt by dcache sync done.

pub fn pro_dcache_sync_int_clr( &mut self ) -> PRO_DCACHE_SYNC_INT_CLR_W<'_, CACHE_SYNC_INT_CTRL_SPEC>

Bit 5 - The bit is used to clear the interrupt by dcache sync done.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual