Type Alias esp32s2::i2s0::conf::R

pub type R = R<CONF_SPEC>;

Register CONF reader

Implementations

impl R

pub fn tx_start(&self) -> TX_START_R

Bit 4 - Set this bit to start transmitting data.

pub fn rx_start(&self) -> RX_START_R

Bit 5 - Set this bit to start receiving data.

pub fn tx_slave_mod(&self) -> TX_SLAVE_MOD_R

Bit 6 - Set this bit to enable slave transmitter mode.

pub fn rx_slave_mod(&self) -> RX_SLAVE_MOD_R

Bit 7 - Set this bit to enable slave receiver mode.

pub fn tx_right_first(&self) -> TX_RIGHT_FIRST_R

Bit 8 - Set this bit to transmit right channel data first.

pub fn rx_right_first(&self) -> RX_RIGHT_FIRST_R

Bit 9 - Set this bit to receive right channel data first.

pub fn tx_msb_shift(&self) -> TX_MSB_SHIFT_R

Bit 10 - Set this bit to enable transmitter in Phillips standard mode.

pub fn rx_msb_shift(&self) -> RX_MSB_SHIFT_R

Bit 11 - Set this bit to enable receiver in Phillips standard mode.

pub fn tx_short_sync(&self) -> TX_SHORT_SYNC_R

Bit 12 - Set this bit to enable transmitter in PCM standard mode.

pub fn rx_short_sync(&self) -> RX_SHORT_SYNC_R

Bit 13 - Set this bit to enable receiver in PCM standard mode.

pub fn tx_mono(&self) -> TX_MONO_R

Bit 14 - Set this bit to enable transmitter in mono mode.

pub fn rx_mono(&self) -> RX_MONO_R

Bit 15 - Set this bit to enable receiver in mono mode.

pub fn tx_msb_right(&self) -> TX_MSB_RIGHT_R

Bit 16 - Set this bit to place right channel data at the MSB in TX FIFO.

pub fn rx_msb_right(&self) -> RX_MSB_RIGHT_R

Bit 17 - Set this bit to place right channel data at the MSB in RX FIFO.

pub fn tx_lsb_first_dma(&self) -> TX_LSB_FIRST_DMA_R

Bit 18 - 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits.

pub fn rx_lsb_first_dma(&self) -> RX_LSB_FIRST_DMA_R

Bit 19 - 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits.

pub fn sig_loopback(&self) -> SIG_LOOPBACK_R

Bit 20 - Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.

pub fn tx_fifo_reset_st(&self) -> TX_FIFO_RESET_ST_R

Bit 21 - I2S TX FIFO reset status. 1: I2S_TX_FIFO_RESET is not completed. 0: I2S_TX_FIFO_RESET is completed.

pub fn rx_fifo_reset_st(&self) -> RX_FIFO_RESET_ST_R

Bit 22 - I2S RX FIFO reset status. 1: I2S_RX_FIFO_RESET is not completed. 0: I2S_RX_FIFO_RESET is completed.

pub fn tx_reset_st(&self) -> TX_RESET_ST_R

Bit 23 - I2S TX reset status. 1: I2S_TX_RESET is not completed. 0: I2S_TX_RESET is completed.

pub fn tx_dma_equal(&self) -> TX_DMA_EQUAL_R

Bit 24 - 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel.

pub fn rx_dma_equal(&self) -> RX_DMA_EQUAL_R

Bit 25 - 1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel.

pub fn pre_req_en(&self) -> PRE_REQ_EN_R

Bit 26 - Set this bit to enable I2S to prepare data earlier.

pub fn tx_big_endian(&self) -> TX_BIG_ENDIAN_R

Bit 27 - I2S TX byte endianness.

pub fn rx_big_endian(&self) -> RX_BIG_ENDIAN_R

Bit 28 - I2S RX byte endianness.

pub fn rx_reset_st(&self) -> RX_RESET_ST_R

Bit 29 - I2S RX reset status. 1: I2S_RX_RESET is not completed. 0: I2S_RX_RESET is completed.