Struct esp32s2::uhci0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 47 fields
    pub conf0: CONF0,
    pub int_raw: INT_RAW,
    pub int_st: INT_ST,
    pub int_ena: INT_ENA,
    pub int_clr: INT_CLR,
    pub dma_out_status: DMA_OUT_STATUS,
    pub dma_out_push: DMA_OUT_PUSH,
    pub dma_in_status: DMA_IN_STATUS,
    pub dma_in_pop: DMA_IN_POP,
    pub dma_out_link: DMA_OUT_LINK,
    pub dma_in_link: DMA_IN_LINK,
    pub conf1: CONF1,
    pub state0: STATE0,
    pub state1: STATE1,
    pub dma_out_eof_des_addr: DMA_OUT_EOF_DES_ADDR,
    pub dma_in_suc_eof_des_addr: DMA_IN_SUC_EOF_DES_ADDR,
    pub dma_in_err_eof_des_addr: DMA_IN_ERR_EOF_DES_ADDR,
    pub dma_out_eof_bfr_des_addr: DMA_OUT_EOF_BFR_DES_ADDR,
    pub ahb_test: AHB_TEST,
    pub dma_in_dscr: DMA_IN_DSCR,
    pub dma_in_dscr_bf0: DMA_IN_DSCR_BF0,
    pub dma_out_dscr: DMA_OUT_DSCR,
    pub dma_out_dscr_bf0: DMA_OUT_DSCR_BF0,
    pub escape_conf: ESCAPE_CONF,
    pub hung_conf: HUNG_CONF,
    pub rx_head: RX_HEAD,
    pub quick_sent: QUICK_SENT,
    pub q0_word0: Q0_WORD0,
    pub q0_word1: Q0_WORD1,
    pub q1_word0: Q1_WORD0,
    pub q1_word1: Q1_WORD1,
    pub q2_word0: Q2_WORD0,
    pub q2_word1: Q2_WORD1,
    pub q3_word0: Q3_WORD0,
    pub q3_word1: Q3_WORD1,
    pub q4_word0: Q4_WORD0,
    pub q4_word1: Q4_WORD1,
    pub q5_word0: Q5_WORD0,
    pub q5_word1: Q5_WORD1,
    pub q6_word0: Q6_WORD0,
    pub q6_word1: Q6_WORD1,
    pub esc_conf0: ESC_CONF0,
    pub esc_conf1: ESC_CONF1,
    pub esc_conf2: ESC_CONF2,
    pub esc_conf3: ESC_CONF3,
    pub pkt_thres: PKT_THRES,
    pub date: DATE,
    /* private fields */

}
Expand description

Register block

Fields§

§conf0: CONF0

0x00 - UHCI configuration register

§int_raw: INT_RAW

0x04 - Raw interrupt status

§int_st: INT_ST

0x08 - Masked interrupt status

§int_ena: INT_ENA

0x0c - Interrupt enable bits

§int_clr: INT_CLR

0x10 - Interrupt clear bits

§dma_out_status: DMA_OUT_STATUS

0x14 - DMA data-output status register

§dma_out_push: DMA_OUT_PUSH

0x18 - Push control register of TX FIFO

§dma_in_status: DMA_IN_STATUS

0x1c - UHCI data-input status register

§dma_in_pop: DMA_IN_POP

0x20 - Pop control register of RX FIFO

§dma_out_link: DMA_OUT_LINK

0x24 - Link descriptor address and control

§dma_in_link: DMA_IN_LINK

0x28 - Link descriptor address and control

§conf1: CONF1

0x2c - UHCI configuration register

§state0: STATE0

0x30 - UHCI decoder status register

§state1: STATE1

0x34 - UHCI encoder status register

§dma_out_eof_des_addr: DMA_OUT_EOF_DES_ADDR

0x38 - Outlink descriptor address when EOF occurs

§dma_in_suc_eof_des_addr: DMA_IN_SUC_EOF_DES_ADDR

0x3c - Inlink descriptor address when EOF occurs

§dma_in_err_eof_des_addr: DMA_IN_ERR_EOF_DES_ADDR

0x40 - Inlink descriptor address when errors occur

§dma_out_eof_bfr_des_addr: DMA_OUT_EOF_BFR_DES_ADDR

0x44 - Outlink descriptor address before the last transmit descriptor

§ahb_test: AHB_TEST

0x48 - AHB test register

§dma_in_dscr: DMA_IN_DSCR

0x4c - The third word of the next receive descriptor

§dma_in_dscr_bf0: DMA_IN_DSCR_BF0

0x50 - The third word of current receive descriptor

§dma_out_dscr: DMA_OUT_DSCR

0x58 - The third word of the next transmit descriptor

§dma_out_dscr_bf0: DMA_OUT_DSCR_BF0

0x5c - The third word of current transmit descriptor

§escape_conf: ESCAPE_CONF

0x64 - Escape character configuration

§hung_conf: HUNG_CONF

0x68 - Timeout configuration

§rx_head: RX_HEAD

0x70 - UHCI packet header register

§quick_sent: QUICK_SENT

0x74 - UHCI quick_sent configuration register

§q0_word0: Q0_WORD0

0x78 - Q0_WORD0 quick_sent register

§q0_word1: Q0_WORD1

0x7c - Q0_WORD1 quick_sent register

§q1_word0: Q1_WORD0

0x80 - Q1_WORD0 quick_sent register

§q1_word1: Q1_WORD1

0x84 - Q1_WORD1 quick_sent register

§q2_word0: Q2_WORD0

0x88 - Q2_WORD0 quick_sent register

§q2_word1: Q2_WORD1

0x8c - Q2_WORD1 quick_sent register

§q3_word0: Q3_WORD0

0x90 - Q3_WORD0 quick_sent register

§q3_word1: Q3_WORD1

0x94 - Q3_WORD1 quick_sent register

§q4_word0: Q4_WORD0

0x98 - Q4_WORD0 quick_sent register

§q4_word1: Q4_WORD1

0x9c - Q4_WORD1 quick_sent register

§q5_word0: Q5_WORD0

0xa0 - Q5_WORD0 quick_sent register

§q5_word1: Q5_WORD1

0xa4 - Q5_WORD1 quick_sent register

§q6_word0: Q6_WORD0

0xa8 - Q6_WORD0 quick_sent register

§q6_word1: Q6_WORD1

0xac - Q6_WORD1 quick_sent register

§esc_conf0: ESC_CONF0

0xb0 - Escape sequence configuration register 0

§esc_conf1: ESC_CONF1

0xb4 - Escape sequence configuration register 1

§esc_conf2: ESC_CONF2

0xb8 - Escape sequence configuration register 2

§esc_conf3: ESC_CONF3

0xbc - Escape sequence configuration register 3

§pkt_thres: PKT_THRES

0xc0 - Configure register for packet length

§date: DATE

0xfc - UHCI version control register

Auto Trait Implementations§

Blanket Implementations§

source§

impl<T> Any for Twhere T: 'static + ?Sized,

source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
source§

impl<T> Borrow<T> for Twhere T: ?Sized,

source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
source§

impl<T> BorrowMut<T> for Twhere T: ?Sized,

source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
source§

impl<T> From<T> for T

source§

fn from(t: T) -> T

Returns the argument unchanged.

source§

impl<T, U> Into<U> for Twhere U: From<T>,

source§

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

source§

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

§

type Error = Infallible

The type returned in the event of a conversion error.
source§

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
source§

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

§

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
source§

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.