Struct esp32s2::timg0::wdtconfig0::W
source · pub struct W(_);
Expand description
Register WDTCONFIG0
writer
Implementations§
source§impl W
impl W
sourcepub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<'_, 12>
pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<'_, 12>
Bit 12 - Reserved.
sourcepub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<'_, 13>
pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<'_, 13>
Bit 13 - WDT reset CPU enable.
sourcepub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<'_, 14>
pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<'_, 14>
Bit 14 - When set, Flash boot protection is enabled.
sourcepub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<'_, 15>
pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<'_, 15>
Bits 15:17 - System reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us.
sourcepub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<'_, 18>
pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<'_, 18>
Bits 18:20 - CPU reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us.
sourcepub fn wdt_level_int_en(&mut self) -> WDT_LEVEL_INT_EN_W<'_, 21>
pub fn wdt_level_int_en(&mut self) -> WDT_LEVEL_INT_EN_W<'_, 21>
Bit 21 - When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt.
sourcepub fn wdt_edge_int_en(&mut self) -> WDT_EDGE_INT_EN_W<'_, 22>
pub fn wdt_edge_int_en(&mut self) -> WDT_EDGE_INT_EN_W<'_, 22>
Bit 22 - When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt.
sourcepub fn wdt_stg3(&mut self) -> WDT_STG3_W<'_, 23>
pub fn wdt_stg3(&mut self) -> WDT_STG3_W<'_, 23>
Bits 23:24 - Stage 3 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.
sourcepub fn wdt_stg2(&mut self) -> WDT_STG2_W<'_, 25>
pub fn wdt_stg2(&mut self) -> WDT_STG2_W<'_, 25>
Bits 25:26 - Stage 2 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.
sourcepub fn wdt_stg1(&mut self) -> WDT_STG1_W<'_, 27>
pub fn wdt_stg1(&mut self) -> WDT_STG1_W<'_, 27>
Bits 27:28 - Stage 1 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.
sourcepub fn wdt_stg0(&mut self) -> WDT_STG0_W<'_, 29>
pub fn wdt_stg0(&mut self) -> WDT_STG0_W<'_, 29>
Bits 29:30 - Stage 0 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.