Struct esp32s2::rtc_cntl::slow_clk_conf::W

pub struct W(_);

Register SLOW_CLK_CONF writer

Implementations

impl W

pub fn ana_clk_div_vld(&mut self) -> ANA_CLK_DIV_VLD_W<'_, 22>

Bit 22 - Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock.

pub fn ana_clk_div(&mut self) -> ANA_CLK_DIV_W<'_, 23>

Bits 23:30 - Set the rtc_clk divider.

pub fn slow_clk_next_edge(&mut self) -> SLOW_CLK_NEXT_EDGE_W<'_, 31>

Bit 31

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SLOW_CLK_CONF_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<SLOW_CLK_CONF_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SLOW_CLK_CONF_SPEC>> for W

fn from(writer: W<SLOW_CLK_CONF_SPEC>) -> Self

Converts to this type from the input type.