pub struct R(_);Expand description
Register FIFO_CONF reader
Implementations§
source§impl R
impl R
sourcepub fn rxfifo_wm_thrhd(&self) -> RXFIFO_WM_THRHD_R
pub fn rxfifo_wm_thrhd(&self) -> RXFIFO_WM_THRHD_R
Bits 0:4 - The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], I2C_RXFIFO_WM_INT_RAW bit will be valid.
sourcepub fn txfifo_wm_thrhd(&self) -> TXFIFO_WM_THRHD_R
pub fn txfifo_wm_thrhd(&self) -> TXFIFO_WM_THRHD_R
Bits 5:9 - The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD[4:0], I2C_TXFIFO_WM_INT_RAW bit will be valid.
sourcepub fn nonfifo_en(&self) -> NONFIFO_EN_R
pub fn nonfifo_en(&self) -> NONFIFO_EN_R
Bit 10 - Set this bit to enable APB non-FIFO mode.
sourcepub fn fifo_addr_cfg_en(&self) -> FIFO_ADDR_CFG_EN_R
pub fn fifo_addr_cfg_en(&self) -> FIFO_ADDR_CFG_EN_R
Bit 11 - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.
sourcepub fn rx_fifo_rst(&self) -> RX_FIFO_RST_R
pub fn rx_fifo_rst(&self) -> RX_FIFO_RST_R
Bit 12 - Set this bit to reset RX FIFO.
sourcepub fn tx_fifo_rst(&self) -> TX_FIFO_RST_R
pub fn tx_fifo_rst(&self) -> TX_FIFO_RST_R
Bit 13 - Set this bit to reset TX FIFO.
sourcepub fn nonfifo_rx_thres(&self) -> NONFIFO_RX_THRES_R
pub fn nonfifo_rx_thres(&self) -> NONFIFO_RX_THRES_R
Bits 14:19 - When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data.
sourcepub fn nonfifo_tx_thres(&self) -> NONFIFO_TX_THRES_R
pub fn nonfifo_tx_thres(&self) -> NONFIFO_TX_THRES_R
Bits 20:25 - When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data.
sourcepub fn fifo_prt_en(&self) -> FIFO_PRT_EN_R
pub fn fifo_prt_en(&self) -> FIFO_PRT_EN_R
Bit 26 - The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty.