Struct esp32s2::spi0::ctrl1::W

pub struct W(_);

Register CTRL1 writer

Implementations

impl W

pub fn clk_mode(&mut self) -> CLK_MODE_W<'_, 0>

Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

pub fn clk_mode_13(&mut self) -> CLK_MODE_13_W<'_, 2>

Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

pub fn rsck_data_out(&mut self) -> RSCK_DATA_OUT_W<'_, 3>

Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

pub fn w16_17_wr_ena(&mut self) -> W16_17_WR_ENA_W<'_, 4>

Bit 4 - 1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state.

pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<'_, 14>

Bits 14:19 - SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CTRL1_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CTRL1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CTRL1_SPEC>> for W

fn from(writer: W<CTRL1_SPEC>) -> Self

Converts to this type from the input type.