Struct esp32s2::extmem::cache_dbg_int_ena::R

pub struct R(_);

Register CACHE_DBG_INT_ENA reader

Implementations

impl R

pub fn cache_dbg_en(&self) -> CACHE_DBG_EN_R

Bit 0 - The bit is used to activate the cache track function. 1: enable, 0: disable.

pub fn ibus_acs_msk_ic_int_ena(&self) -> IBUS_ACS_MSK_IC_INT_ENA_R

Bit 2 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.

pub fn ibus_cnt_ovf_int_ena(&self) -> IBUS_CNT_OVF_INT_ENA_R

Bit 3 - The bit is used to enable interrupt by ibus counter overflow.

pub fn ic_sync_size_fault_int_ena(&self) -> IC_SYNC_SIZE_FAULT_INT_ENA_R

Bit 4 - The bit is used to enable interrupt by manual sync configurations fault.

pub fn ic_preload_size_fault_int_ena(&self) -> IC_PRELOAD_SIZE_FAULT_INT_ENA_R

Bit 5 - The bit is used to enable interrupt by manual pre-load configurations fault.

pub fn icache_reject_int_ena(&self) -> ICACHE_REJECT_INT_ENA_R

Bit 6 - The bit is used to enable interrupt by authentication fail.

pub fn icache_set_preload_ilg_int_ena(&self) -> ICACHE_SET_PRELOAD_ILG_INT_ENA_R

Bit 7 - The bit is used to enable interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.

pub fn icache_set_sync_ilg_int_ena(&self) -> ICACHE_SET_SYNC_ILG_INT_ENA_R

Bit 8 - The bit is used to enable interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.

pub fn icache_set_lock_ilg_int_ena(&self) -> ICACHE_SET_LOCK_ILG_INT_ENA_R

Bit 9 - The bit is used to enable interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.

pub fn dbus_acs_msk_dc_int_ena(&self) -> DBUS_ACS_MSK_DC_INT_ENA_R

Bit 10 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.

pub fn dbus_cnt_ovf_int_ena(&self) -> DBUS_CNT_OVF_INT_ENA_R

Bit 11 - The bit is used to enable interrupt by dbus counter overflow.

pub fn dc_sync_size_fault_int_ena(&self) -> DC_SYNC_SIZE_FAULT_INT_ENA_R

Bit 12 - The bit is used to enable interrupt by manual sync configurations fault.

pub fn dc_preload_size_fault_int_ena(&self) -> DC_PRELOAD_SIZE_FAULT_INT_ENA_R

Bit 13 - The bit is used to enable interrupt by manual pre-load configurations fault.

pub fn dcache_write_flash_int_ena(&self) -> DCACHE_WRITE_FLASH_INT_ENA_R

Bit 14 - The bit is used to enable interrupt by dcache trying to write flash.

pub fn dcache_reject_int_ena(&self) -> DCACHE_REJECT_INT_ENA_R

Bit 15 - The bit is used to enable interrupt by authentication fail.

pub fn dcache_set_preload_ilg_int_ena(&self) -> DCACHE_SET_PRELOAD_ILG_INT_ENA_R

Bit 16 - The bit is used to enable interrupt by illegal writing preload registers of dcache while dcache is busy to issue lock,sync and pre-load operations.

pub fn dcache_set_sync_ilg_int_ena(&self) -> DCACHE_SET_SYNC_ILG_INT_ENA_R

Bit 17 - The bit is used to enable interrupt by illegal writing sync registers of dcache while dcache is busy to issue lock,sync and pre-load operations.

pub fn dcache_set_lock_ilg_int_ena(&self) -> DCACHE_SET_LOCK_ILG_INT_ENA_R

Bit 18 - The bit is used to enable interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations.

pub fn mmu_entry_fault_int_ena(&self) -> MMU_ENTRY_FAULT_INT_ENA_R

Bit 19 - The bit is used to enable interrupt by mmu entry fault.

Methods from Deref<Target = R<CACHE_DBG_INT_ENA_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_DBG_INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CACHE_DBG_INT_ENA_SPEC>> for R

fn from(reader: R<CACHE_DBG_INT_ENA_SPEC>) -> Self

Converts to this type from the input type.