Struct esp32s2::uhci0::conf0::R

pub struct R(_);

Register CONF0 reader

Implementations

impl R

pub fn in_rst(&self) -> IN_RST_R

Bit 0 - Set this bit to reset in DMA FSM.

pub fn out_rst(&self) -> OUT_RST_R

Bit 1 - Set this bit to reset out DMA FSM.

pub fn ahbm_fifo_rst(&self) -> AHBM_FIFO_RST_R

Bit 2 - Set this bit to reset AHB interface cmdFIFO of DMA.

pub fn ahbm_rst(&self) -> AHBM_RST_R

Bit 3 - Set this bit to reset AHB interface of DMA.

pub fn in_loop_test(&self) -> IN_LOOP_TEST_R

Bit 4 - Reserved.

pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R

Bit 5 - Reserved.

pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R

Bit 6 - Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted.

pub fn out_no_restart_clr(&self) -> OUT_NO_RESTART_CLR_R

Bit 7 - Reserved.

pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R

Bit 8 - This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. 1: When DMA has popped all data from FIFO. 0: When AHB has pushed all data to FIFO.

pub fn uart0_ce(&self) -> UART0_CE_R

Bit 9 - Set this bit to link up UHCI and UART0.

pub fn uart1_ce(&self) -> UART1_CE_R

Bit 10 - Set this bit to link up UHCI and UART1.

pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R

Bit 12 - This register is used to specify DMA transmit descriptor transfer mode. 1: burst mode. 0: byte mode.

pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R

Bit 13 - This register is used to specify DMA receive descriptor transfer mode. 1: burst mode. 0: byte mode.

pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R

Bit 15 - 1: UHCI transmitted data would be write back into DMA INFIFO.

pub fn seper_en(&self) -> SEPER_EN_R

Bit 16 - Set this bit to separate the data frame using a special character.

pub fn head_en(&self) -> HEAD_EN_R

Bit 17 - Set this bit to encode the data packet with a formatting header.

pub fn crc_rec_en(&self) -> CRC_REC_EN_R

Bit 18 - Set this bit to enable UHCI to receive the 16 bit CRC.

pub fn uart_idle_eof_en(&self) -> UART_IDLE_EOF_EN_R

Bit 19 - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.

pub fn len_eof_en(&self) -> LEN_EOF_EN_R

Bit 20 - If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0.

pub fn encode_crc_en(&self) -> ENCODE_CRC_EN_R

Bit 21 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload.

pub fn clk_en(&self) -> CLK_EN_R

Bit 22 - 1: Force clock on for registers. 0: Support clock only when application writes registers.

pub fn uart_rx_brk_eof_en(&self) -> UART_RX_BRK_EOF_EN_R

Bit 23 - If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART.

Methods from Deref<Target = R<CONF0_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CONF0_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CONF0_SPEC>> for R

fn from(reader: R<CONF0_SPEC>) -> Self

Converts to this type from the input type.