pub struct W(_);
Expand description
Register CONF1
writer
Implementations§
source§impl W
impl W
sourcepub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<'_, 0>
pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<'_, 0>
Bits 0:8 - An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value.
sourcepub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<'_, 9>
pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<'_, 9>
Bits 9:17 - An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register’s value.
sourcepub fn rx_tout_flow_dis(&mut self) -> RX_TOUT_FLOW_DIS_W<'_, 29>
pub fn rx_tout_flow_dis(&mut self) -> RX_TOUT_FLOW_DIS_W<'_, 29>
Bit 29 - Set this bit to stop accumulating idle_cnt when hardware flow control works.
sourcepub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W<'_, 30>
pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W<'_, 30>
Bit 30 - This is the flow enable bit for UART receiver. 1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control.
sourcepub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W<'_, 31>
pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W<'_, 31>
Bit 31 - This is the enable bit for UART receiver’s timeout function.