pub struct W(_);
Expand description
Register LCD_D_NUM
writer
Implementations§
source§impl W
impl W
sourcepub fn d_dqs_num(&mut self) -> D_DQS_NUM_W<'_, 0>
pub fn d_dqs_num(&mut self) -> D_DQS_NUM_W<'_, 0>
Bits 0:1 - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn d_cd_num(&mut self) -> D_CD_NUM_W<'_, 2>
pub fn d_cd_num(&mut self) -> D_CD_NUM_W<'_, 2>
Bits 2:3 - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn d_de_num(&mut self) -> D_DE_NUM_W<'_, 4>
pub fn d_de_num(&mut self) -> D_DE_NUM_W<'_, 4>
Bits 4:5 - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn d_hsync_num(&mut self) -> D_HSYNC_NUM_W<'_, 6>
pub fn d_hsync_num(&mut self) -> D_HSYNC_NUM_W<'_, 6>
Bits 6:7 - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn d_vsync_num(&mut self) -> D_VSYNC_NUM_W<'_, 8>
pub fn d_vsync_num(&mut self) -> D_VSYNC_NUM_W<'_, 8>
Bits 8:9 - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.