Struct esp32s2::dedicated_gpio::intr_rcgn::W

pub struct W(_);

Register INTR_RCGN writer

Implementations

impl W

pub fn intr_mode_ch0(&mut self) -> INTR_MODE_CH0_W<'_, 0>

Bits 0:2 - Configure channel 0 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub fn intr_mode_ch1(&mut self) -> INTR_MODE_CH1_W<'_, 3>

Bits 3:5 - Configure channel 1 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub fn intr_mode_ch2(&mut self) -> INTR_MODE_CH2_W<'_, 6>

Bits 6:8 - Configure channel 2 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub fn intr_mode_ch3(&mut self) -> INTR_MODE_CH3_W<'_, 9>

Bits 9:11 - Configure channel 3 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub fn intr_mode_ch4(&mut self) -> INTR_MODE_CH4_W<'_, 12>

Bits 12:14 - Configure channel 4 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub fn intr_mode_ch5(&mut self) -> INTR_MODE_CH5_W<'_, 15>

Bits 15:17 - Configure channel 5 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub fn intr_mode_ch6(&mut self) -> INTR_MODE_CH6_W<'_, 18>

Bits 18:20 - Configure channel 6 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub fn intr_mode_ch7(&mut self) -> INTR_MODE_CH7_W<'_, 21>

Bits 21:23 - Configure channel 7 interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<INTR_RCGN_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<INTR_RCGN_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<INTR_RCGN_SPEC>> for W

fn from(writer: W<INTR_RCGN_SPEC>) -> Self

Converts to this type from the input type.