pub struct W(_);
Expand description
Register CLOCK
writer
Implementations§
source§impl W
impl W
sourcepub fn clkcnt_l(&mut self) -> CLKCNT_L_W<'_, 0>
pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<'_, 0>
Bits 0:5 - In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state.
sourcepub fn clkcnt_h(&mut self) -> CLKCNT_H_W<'_, 6>
pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<'_, 6>
Bits 6:11 - In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
sourcepub fn clkcnt_n(&mut self) -> CLKCNT_N_W<'_, 12>
pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<'_, 12>
Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state.
sourcepub fn clkdiv_pre(&mut self) -> CLKDIV_PRE_W<'_, 18>
pub fn clkdiv_pre(&mut self) -> CLKDIV_PRE_W<'_, 18>
Bits 18:30 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
sourcepub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<'_, 31>
pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<'_, 31>
Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.