Struct esp32s2::extmem::cache_dbg_status1::R

pub struct R(_);

Register CACHE_DBG_STATUS1 reader

Implementations

impl R

pub fn dbus0_acs_msk_dcache_st(&self) -> DBUS0_ACS_MSK_DCACHE_ST_R

Bit 0 - The bit is used to indicate interrupt by cpu access dcache while the dbus0 is disabled or dcache is disabled which include speculative access.

pub fn dbus1_acs_msk_dcache_st(&self) -> DBUS1_ACS_MSK_DCACHE_ST_R

Bit 1 - The bit is used to indicate interrupt by cpu access dcache while the dbus1 is disabled or dcache is disabled which include speculative access.

pub fn dbus2_acs_msk_dcache_st(&self) -> DBUS2_ACS_MSK_DCACHE_ST_R

Bit 2 - The bit is used to indicate interrupt by cpu access dcache while the dbus2 is disabled or dcache is disabled which include speculative access.

pub fn dbus0_acs_cnt_ovf_st(&self) -> DBUS0_ACS_CNT_OVF_ST_R

Bit 4 - The bit is used to indicate interrupt by dbus0 counter overflow.

pub fn dbus1_acs_cnt_ovf_st(&self) -> DBUS1_ACS_CNT_OVF_ST_R

Bit 5 - The bit is used to indicate interrupt by dbus1 counter overflow.

pub fn dbus2_acs_cnt_ovf_st(&self) -> DBUS2_ACS_CNT_OVF_ST_R

Bit 6 - The bit is used to indicate interrupt by dbus2 counter overflow.

pub fn dbus0_acs_miss_cnt_ovf_st(&self) -> DBUS0_ACS_MISS_CNT_OVF_ST_R

Bit 8 - The bit is used to indicate interrupt by dbus0 miss counter overflow.

pub fn dbus1_acs_miss_cnt_ovf_st(&self) -> DBUS1_ACS_MISS_CNT_OVF_ST_R

Bit 9 - The bit is used to indicate interrupt by dbus1 miss counter overflow.

pub fn dbus2_acs_miss_cnt_ovf_st(&self) -> DBUS2_ACS_MISS_CNT_OVF_ST_R

Bit 10 - The bit is used to indicate interrupt by dbus2 miss counter overflow.

pub fn dbus0_acs_wb_cnt_ovf_st(&self) -> DBUS0_ACS_WB_CNT_OVF_ST_R

Bit 12 - The bit is used to indicate interrupt by dbus0 eviction counter overflow.

pub fn dbus1_acs_wb_cnt_ovf_st(&self) -> DBUS1_ACS_WB_CNT_OVF_ST_R

Bit 13 - The bit is used to indicate interrupt by dbus1 eviction counter overflow.

pub fn dbus2_acs_wb_cnt_ovf_st(&self) -> DBUS2_ACS_WB_CNT_OVF_ST_R

Bit 14 - The bit is used to indicate interrupt by dbus2 eviction counter overflow.

pub fn dbus0_abandon_cnt_ovf_st(&self) -> DBUS0_ABANDON_CNT_OVF_ST_R

Bit 16 - The bit is used to indicate interrupt by dbus0 abandon counter overflow.

pub fn dbus1_abandon_cnt_ovf_st(&self) -> DBUS1_ABANDON_CNT_OVF_ST_R

Bit 17 - The bit is used to indicate interrupt by dbus1 abandon counter overflow.

pub fn dbus2_abandon_cnt_ovf_st(&self) -> DBUS2_ABANDON_CNT_OVF_ST_R

Bit 18 - The bit is used to indicate interrupt by dbus2 abandon counter overflow.

pub fn dc_preload_miss_cnt_ovf_st(&self) -> DC_PRELOAD_MISS_CNT_OVF_ST_R

Bit 20 - The bit is used to indicate interrupt by pre-load miss counter overflow.

pub fn dc_preload_evict_cnt_ovf_st(&self) -> DC_PRELOAD_EVICT_CNT_OVF_ST_R

Bit 21 - The bit is used to indicate interrupt by pre-load eviction counter overflow.

pub fn dc_preload_cnt_ovf_st(&self) -> DC_PRELOAD_CNT_OVF_ST_R

Bit 22 - The bit is used to indicate interrupt by pre-load counter overflow.

pub fn dc_sync_size_fault_st(&self) -> DC_SYNC_SIZE_FAULT_ST_R

Bit 23 - The bit is used to indicate interrupt by manual sync configurations fault.

pub fn dc_preload_size_fault_st(&self) -> DC_PRELOAD_SIZE_FAULT_ST_R

Bit 24 - The bit is used to indicate interrupt by manual pre-load configurations fault.

pub fn dcache_write_flash_st(&self) -> DCACHE_WRITE_FLASH_ST_R

Bit 25 - The bit is used to indicate interrupt by dcache trying to write flash.

pub fn dcache_reject_st(&self) -> DCACHE_REJECT_ST_R

Bit 26 - The bit is used to indicate interrupt by authentication fail.

pub fn dcache_set_preload_ilg_st(&self) -> DCACHE_SET_PRELOAD_ILG_ST_R

Bit 27 - The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.

pub fn dcache_set_sync_ilg_st(&self) -> DCACHE_SET_SYNC_ILG_ST_R

Bit 28 - The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.

pub fn dcache_set_lock_ilg_st(&self) -> DCACHE_SET_LOCK_ILG_ST_R

Bit 29 - The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.

pub fn mmu_entry_fault_st(&self) -> MMU_ENTRY_FAULT_ST_R

Bit 30 - The bit is used to indicate interrupt by mmu entry fault.

Methods from Deref<Target = R<CACHE_DBG_STATUS1_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_DBG_STATUS1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CACHE_DBG_STATUS1_SPEC>> for R

fn from(reader: R<CACHE_DBG_STATUS1_SPEC>) -> Self

Converts to this type from the input type.