Struct esp32s2::extmem::cache_dbg_int_clr::W

pub struct W(_);

Register CACHE_DBG_INT_CLR writer

Implementations

impl W

pub fn ibus_acs_msk_ic_int_clr(&mut self) -> IBUS_ACS_MSK_IC_INT_CLR_W<'_, 0>

Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.

pub fn ibus_cnt_ovf_int_clr(&mut self) -> IBUS_CNT_OVF_INT_CLR_W<'_, 1>

Bit 1 - The bit is used to clear interrupt by ibus counter overflow.

pub fn ic_sync_size_fault_int_clr( &mut self ) -> IC_SYNC_SIZE_FAULT_INT_CLR_W<'_, 2>

Bit 2 - The bit is used to clear interrupt by manual sync configurations fault.

pub fn ic_preload_size_fault_int_clr( &mut self ) -> IC_PRELOAD_SIZE_FAULT_INT_CLR_W<'_, 3>

Bit 3 - The bit is used to clear interrupt by manual pre-load configurations fault.

pub fn icache_reject_int_clr(&mut self) -> ICACHE_REJECT_INT_CLR_W<'_, 4>

Bit 4 - The bit is used to clear interrupt by authentication fail.

pub fn icache_set_ilg_int_clr(&mut self) -> ICACHE_SET_ILG_INT_CLR_W<'_, 5>

Bit 5 - The bit is used to clear interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.

pub fn dbus_acs_msk_dc_int_clr(&mut self) -> DBUS_ACS_MSK_DC_INT_CLR_W<'_, 6>

Bit 6 - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.

pub fn dbus_cnt_ovf_int_clr(&mut self) -> DBUS_CNT_OVF_INT_CLR_W<'_, 7>

Bit 7 - The bit is used to clear interrupt by dbus counter overflow.

pub fn dc_sync_size_fault_int_clr( &mut self ) -> DC_SYNC_SIZE_FAULT_INT_CLR_W<'_, 8>

Bit 8 - The bit is used to clear interrupt by manual sync configurations fault.

pub fn dc_preload_size_fault_int_clr( &mut self ) -> DC_PRELOAD_SIZE_FAULT_INT_CLR_W<'_, 9>

Bit 9 - The bit is used to clear interrupt by manual pre-load configurations fault.

pub fn dcache_write_flash_int_clr( &mut self ) -> DCACHE_WRITE_FLASH_INT_CLR_W<'_, 10>

Bit 10 - The bit is used to clear interrupt by dcache trying to write flash.

pub fn dcache_reject_int_clr(&mut self) -> DCACHE_REJECT_INT_CLR_W<'_, 11>

Bit 11 - The bit is used to clear interrupt by authentication fail.

pub fn dcache_set_ilg_int_clr(&mut self) -> DCACHE_SET_ILG_INT_CLR_W<'_, 12>

Bit 12 - The bit is used to clear interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations.

pub fn mmu_entry_fault_int_clr(&mut self) -> MMU_ENTRY_FAULT_INT_CLR_W<'_, 13>

Bit 13 - The bit is used to clear interrupt by mmu entry fault.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_DBG_INT_CLR_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_DBG_INT_CLR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CACHE_DBG_INT_CLR_SPEC>> for W

fn from(writer: W<CACHE_DBG_INT_CLR_SPEC>) -> Self

Converts to this type from the input type.