Module esp32s2::spi0::lcd_d_num

LCD delay mode

Structs

LCD_D_NUM_SPEC

LCD delay mode

R

Register LCD_D_NUM reader

W

Register LCD_D_NUM writer

Type Definitions

D_CD_NUM_R

Field D_CD_NUM reader - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_CD_NUM_W

Field D_CD_NUM writer - the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_DE_NUM_R

Field D_DE_NUM reader - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_DE_NUM_W

Field D_DE_NUM writer - the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_DQS_NUM_R

Field D_DQS_NUM reader - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_DQS_NUM_W

Field D_DQS_NUM writer - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_HSYNC_NUM_R

Field D_HSYNC_NUM reader - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_HSYNC_NUM_W

Field D_HSYNC_NUM writer - the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_VSYNC_NUM_R

Field D_VSYNC_NUM reader - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

D_VSYNC_NUM_W

Field D_VSYNC_NUM writer - the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.