Struct esp32s2::extmem::RegisterBlock

source ·

#[repr(C)]
pub struct RegisterBlock {Show 80 fields
    pub pro_dcache_ctrl: PRO_DCACHE_CTRL,
    pub pro_dcache_ctrl1: PRO_DCACHE_CTRL1,
    pub pro_dcache_tag_power_ctrl: PRO_DCACHE_TAG_POWER_CTRL,
    pub pro_dcache_lock0_addr: PRO_DCACHE_LOCK0_ADDR,
    pub pro_dcache_lock0_size: PRO_DCACHE_LOCK0_SIZE,
    pub pro_dcache_lock1_addr: PRO_DCACHE_LOCK1_ADDR,
    pub pro_dcache_lock1_size: PRO_DCACHE_LOCK1_SIZE,
    pub pro_dcache_mem_sync0: PRO_DCACHE_MEM_SYNC0,
    pub pro_dcache_mem_sync1: PRO_DCACHE_MEM_SYNC1,
    pub pro_dcache_preload_addr: PRO_DCACHE_PRELOAD_ADDR,
    pub pro_dcache_preload_size: PRO_DCACHE_PRELOAD_SIZE,
    pub pro_dcache_autoload_cfg: PRO_DCACHE_AUTOLOAD_CFG,
    pub pro_dcache_autoload_section0_addr: PRO_DCACHE_AUTOLOAD_SECTION0_ADDR,
    pub pro_dcache_autoload_section0_size: PRO_DCACHE_AUTOLOAD_SECTION0_SIZE,
    pub pro_dcache_autoload_section1_addr: PRO_DCACHE_AUTOLOAD_SECTION1_ADDR,
    pub pro_dcache_autoload_section1_size: PRO_DCACHE_AUTOLOAD_SECTION1_SIZE,
    pub pro_icache_ctrl: PRO_ICACHE_CTRL,
    pub pro_icache_ctrl1: PRO_ICACHE_CTRL1,
    pub pro_icache_tag_power_ctrl: PRO_ICACHE_TAG_POWER_CTRL,
    pub pro_icache_lock0_addr: PRO_ICACHE_LOCK0_ADDR,
    pub pro_icache_lock0_size: PRO_ICACHE_LOCK0_SIZE,
    pub pro_icache_lock1_addr: PRO_ICACHE_LOCK1_ADDR,
    pub pro_icache_lock1_size: PRO_ICACHE_LOCK1_SIZE,
    pub pro_icache_mem_sync0: PRO_ICACHE_MEM_SYNC0,
    pub pro_icache_mem_sync1: PRO_ICACHE_MEM_SYNC1,
    pub pro_icache_preload_addr: PRO_ICACHE_PRELOAD_ADDR,
    pub pro_icache_preload_size: PRO_ICACHE_PRELOAD_SIZE,
    pub pro_icache_autoload_cfg: PRO_ICACHE_AUTOLOAD_CFG,
    pub pro_icache_autoload_section0_addr: PRO_ICACHE_AUTOLOAD_SECTION0_ADDR,
    pub pro_icache_autoload_section0_size: PRO_ICACHE_AUTOLOAD_SECTION0_SIZE,
    pub pro_icache_autoload_section1_addr: PRO_ICACHE_AUTOLOAD_SECTION1_ADDR,
    pub pro_icache_autoload_section1_size: PRO_ICACHE_AUTOLOAD_SECTION1_SIZE,
    pub ic_preload_cnt: IC_PRELOAD_CNT,
    pub ic_preload_miss_cnt: IC_PRELOAD_MISS_CNT,
    pub ibus2_abandon_cnt: IBUS2_ABANDON_CNT,
    pub ibus1_abandon_cnt: IBUS1_ABANDON_CNT,
    pub ibus0_abandon_cnt: IBUS0_ABANDON_CNT,
    pub ibus2_acs_miss_cnt: IBUS2_ACS_MISS_CNT,
    pub ibus1_acs_miss_cnt: IBUS1_ACS_MISS_CNT,
    pub ibus0_acs_miss_cnt: IBUS0_ACS_MISS_CNT,
    pub ibus2_acs_cnt: IBUS2_ACS_CNT,
    pub ibus1_acs_cnt: IBUS1_ACS_CNT,
    pub ibus0_acs_cnt: IBUS0_ACS_CNT,
    pub dc_preload_cnt: DC_PRELOAD_CNT,
    pub dc_preload_evict_cnt: DC_PRELOAD_EVICT_CNT,
    pub dc_preload_miss_cnt: DC_PRELOAD_MISS_CNT,
    pub dbus2_abandon_cnt: DBUS2_ABANDON_CNT,
    pub dbus1_abandon_cnt: DBUS1_ABANDON_CNT,
    pub dbus0_abandon_cnt: DBUS0_ABANDON_CNT,
    pub dbus2_acs_wb_cnt: DBUS2_ACS_WB_CNT,
    pub dbus1_acs_wb_cnt: DBUS1_ACS_WB_CNT,
    pub dbus0_acs_wb_cnt: DBUS0_ACS_WB_CNT,
    pub dbus2_acs_miss_cnt: DBUS2_ACS_MISS_CNT,
    pub dbus1_acs_miss_cnt: DBUS1_ACS_MISS_CNT,
    pub dbus0_acs_miss_cnt: DBUS0_ACS_MISS_CNT,
    pub dbus2_acs_cnt: DBUS2_ACS_CNT,
    pub dbus1_acs_cnt: DBUS1_ACS_CNT,
    pub dbus0_acs_cnt: DBUS0_ACS_CNT,
    pub cache_dbg_int_ena: CACHE_DBG_INT_ENA,
    pub cache_dbg_int_clr: CACHE_DBG_INT_CLR,
    pub cache_dbg_status0: CACHE_DBG_STATUS0,
    pub cache_dbg_status1: CACHE_DBG_STATUS1,
    pub pro_cache_acs_cnt_clr: PRO_CACHE_ACS_CNT_CLR,
    pub pro_dcache_reject_st: PRO_DCACHE_REJECT_ST,
    pub pro_dcache_reject_vaddr: PRO_DCACHE_REJECT_VADDR,
    pub pro_icache_reject_st: PRO_ICACHE_REJECT_ST,
    pub pro_icache_reject_vaddr: PRO_ICACHE_REJECT_VADDR,
    pub pro_cache_mmu_fault_content: PRO_CACHE_MMU_FAULT_CONTENT,
    pub pro_cache_mmu_fault_vaddr: PRO_CACHE_MMU_FAULT_VADDR,
    pub pro_cache_wrap_around_ctrl: PRO_CACHE_WRAP_AROUND_CTRL,
    pub pro_cache_mmu_power_ctrl: PRO_CACHE_MMU_POWER_CTRL,
    pub pro_cache_state: PRO_CACHE_STATE,
    pub cache_encrypt_decrypt_record_disable: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE,
    pub cache_encrypt_decrypt_clk_force_on: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON,
    pub cache_bridge_arbiter_ctrl: CACHE_BRIDGE_ARBITER_CTRL,
    pub cache_preload_int_ctrl: CACHE_PRELOAD_INT_CTRL,
    pub cache_sync_int_ctrl: CACHE_SYNC_INT_CTRL,
    pub cache_conf_misc: CACHE_CONF_MISC,
    pub clock_gate: CLOCK_GATE,
    pub pro_extmem_reg_date: PRO_EXTMEM_REG_DATE,
    /* private fields */
}

Expand description

Register block

Fields§

§pro_dcache_ctrl: PRO_DCACHE_CTRL

0x00 - register description

§pro_dcache_ctrl1: PRO_DCACHE_CTRL1

0x04 - register description

§pro_dcache_tag_power_ctrl: PRO_DCACHE_TAG_POWER_CTRL

0x08 - register description

§pro_dcache_lock0_addr: PRO_DCACHE_LOCK0_ADDR

0x0c - register description

§pro_dcache_lock0_size: PRO_DCACHE_LOCK0_SIZE

0x10 - register description

§pro_dcache_lock1_addr: PRO_DCACHE_LOCK1_ADDR

0x14 - register description

§pro_dcache_lock1_size: PRO_DCACHE_LOCK1_SIZE

0x18 - register description

§pro_dcache_mem_sync0: PRO_DCACHE_MEM_SYNC0

0x1c - register description

§pro_dcache_mem_sync1: PRO_DCACHE_MEM_SYNC1

0x20 - register description

§pro_dcache_preload_addr: PRO_DCACHE_PRELOAD_ADDR

0x24 - register description

§pro_dcache_preload_size: PRO_DCACHE_PRELOAD_SIZE

0x28 - register description

§pro_dcache_autoload_cfg: PRO_DCACHE_AUTOLOAD_CFG

0x2c - register description

§pro_dcache_autoload_section0_addr: PRO_DCACHE_AUTOLOAD_SECTION0_ADDR

0x30 - register description

§pro_dcache_autoload_section0_size: PRO_DCACHE_AUTOLOAD_SECTION0_SIZE

0x34 - register description

§pro_dcache_autoload_section1_addr: PRO_DCACHE_AUTOLOAD_SECTION1_ADDR

0x38 - register description

§pro_dcache_autoload_section1_size: PRO_DCACHE_AUTOLOAD_SECTION1_SIZE

0x3c - register description

§pro_icache_ctrl: PRO_ICACHE_CTRL

0x40 - register description

§pro_icache_ctrl1: PRO_ICACHE_CTRL1

0x44 - register description

§pro_icache_tag_power_ctrl: PRO_ICACHE_TAG_POWER_CTRL

0x48 - register description

§pro_icache_lock0_addr: PRO_ICACHE_LOCK0_ADDR

0x4c - register description

§pro_icache_lock0_size: PRO_ICACHE_LOCK0_SIZE

0x50 - register description

§pro_icache_lock1_addr: PRO_ICACHE_LOCK1_ADDR

0x54 - register description

§pro_icache_lock1_size: PRO_ICACHE_LOCK1_SIZE

0x58 - register description

§pro_icache_mem_sync0: PRO_ICACHE_MEM_SYNC0

0x5c - register description

§pro_icache_mem_sync1: PRO_ICACHE_MEM_SYNC1

0x60 - register description

§pro_icache_preload_addr: PRO_ICACHE_PRELOAD_ADDR

0x64 - register description

§pro_icache_preload_size: PRO_ICACHE_PRELOAD_SIZE

0x68 - register description

§pro_icache_autoload_cfg: PRO_ICACHE_AUTOLOAD_CFG

0x6c - register description

§pro_icache_autoload_section0_addr: PRO_ICACHE_AUTOLOAD_SECTION0_ADDR

0x70 - register description

§pro_icache_autoload_section0_size: PRO_ICACHE_AUTOLOAD_SECTION0_SIZE

0x74 - register description

§pro_icache_autoload_section1_addr: PRO_ICACHE_AUTOLOAD_SECTION1_ADDR

0x78 - register description

§pro_icache_autoload_section1_size: PRO_ICACHE_AUTOLOAD_SECTION1_SIZE

0x7c - register description

§ic_preload_cnt: IC_PRELOAD_CNT

0x80 - register description

§ic_preload_miss_cnt: IC_PRELOAD_MISS_CNT

0x84 - register description

§ibus2_abandon_cnt: IBUS2_ABANDON_CNT

0x88 - register description

§ibus1_abandon_cnt: IBUS1_ABANDON_CNT

0x8c - register description

§ibus0_abandon_cnt: IBUS0_ABANDON_CNT

0x90 - register description

§ibus2_acs_miss_cnt: IBUS2_ACS_MISS_CNT

0x94 - register description

§ibus1_acs_miss_cnt: IBUS1_ACS_MISS_CNT

0x98 - register description

§ibus0_acs_miss_cnt: IBUS0_ACS_MISS_CNT

0x9c - register description

§ibus2_acs_cnt: IBUS2_ACS_CNT

0xa0 - register description

§ibus1_acs_cnt: IBUS1_ACS_CNT

0xa4 - register description

§ibus0_acs_cnt: IBUS0_ACS_CNT

0xa8 - register description

§dc_preload_cnt: DC_PRELOAD_CNT

0xac - register description

§dc_preload_evict_cnt: DC_PRELOAD_EVICT_CNT

0xb0 - register description

§dc_preload_miss_cnt: DC_PRELOAD_MISS_CNT

0xb4 - register description

§dbus2_abandon_cnt: DBUS2_ABANDON_CNT

0xb8 - register description

§dbus1_abandon_cnt: DBUS1_ABANDON_CNT

0xbc - register description

§dbus0_abandon_cnt: DBUS0_ABANDON_CNT

0xc0 - register description

§dbus2_acs_wb_cnt: DBUS2_ACS_WB_CNT

0xc4 - register description

§dbus1_acs_wb_cnt: DBUS1_ACS_WB_CNT

0xc8 - register description

§dbus0_acs_wb_cnt: DBUS0_ACS_WB_CNT

0xcc - register description

§dbus2_acs_miss_cnt: DBUS2_ACS_MISS_CNT

0xd0 - register description

§dbus1_acs_miss_cnt: DBUS1_ACS_MISS_CNT

0xd4 - register description

§dbus0_acs_miss_cnt: DBUS0_ACS_MISS_CNT

0xd8 - register description

§dbus2_acs_cnt: DBUS2_ACS_CNT

0xdc - register description

§dbus1_acs_cnt: DBUS1_ACS_CNT

0xe0 - register description

§dbus0_acs_cnt: DBUS0_ACS_CNT

0xe4 - register description

§cache_dbg_int_ena: CACHE_DBG_INT_ENA

0xe8 - register description

§cache_dbg_int_clr: CACHE_DBG_INT_CLR

0xec - register description

§cache_dbg_status0: CACHE_DBG_STATUS0

0xf0 - register description

§cache_dbg_status1: CACHE_DBG_STATUS1

0xf4 - register description

§pro_cache_acs_cnt_clr: PRO_CACHE_ACS_CNT_CLR

0xf8 - register description

§pro_dcache_reject_st: PRO_DCACHE_REJECT_ST

0xfc - register description

§pro_dcache_reject_vaddr: PRO_DCACHE_REJECT_VADDR

0x100 - register description

§pro_icache_reject_st: PRO_ICACHE_REJECT_ST

0x104 - register description

§pro_icache_reject_vaddr: PRO_ICACHE_REJECT_VADDR

0x108 - register description

§pro_cache_mmu_fault_content: PRO_CACHE_MMU_FAULT_CONTENT

0x10c - register description

§pro_cache_mmu_fault_vaddr: PRO_CACHE_MMU_FAULT_VADDR

0x110 - register description

§pro_cache_wrap_around_ctrl: PRO_CACHE_WRAP_AROUND_CTRL

0x114 - register description

§pro_cache_mmu_power_ctrl: PRO_CACHE_MMU_POWER_CTRL

0x118 - register description

§pro_cache_state: PRO_CACHE_STATE

0x11c - register description

§cache_encrypt_decrypt_record_disable: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE

0x120 - register description

§cache_encrypt_decrypt_clk_force_on: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON

0x124 - register description

§cache_bridge_arbiter_ctrl: CACHE_BRIDGE_ARBITER_CTRL

0x128 - register description

§cache_preload_int_ctrl: CACHE_PRELOAD_INT_CTRL

0x12c - register description

§cache_sync_int_ctrl: CACHE_SYNC_INT_CTRL

0x130 - register description

§cache_conf_misc: CACHE_CONF_MISC

0x134 - register description

§clock_gate: CLOCK_GATE

0x138 - register description

§pro_extmem_reg_date: PRO_EXTMEM_REG_DATE

0x3fc - register description

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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impl<T> Any for Twhere
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fn type_id(&self) -> TypeId

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Returns the argument unchanged.

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom for Twhere
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type Error = Infallible

The type returned in the event of a conversion error.

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fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

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impl<T, U> TryInto for Twhere
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type Error = >::Error

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fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct esp32s2::extmem::RegisterBlock

Fields§

Auto Trait Implementations§

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere
T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere
T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere
T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere
U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere
U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere
U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct esp32s2::extmem::RegisterBlock

Fields§

Auto Trait Implementations§

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

impl<T> Any for Twhere
T: 'static + ?Sized,

impl<T> Borrow<T> for Twhere
T: ?Sized,

impl<T> BorrowMut<T> for Twhere
T: ?Sized,

impl<T, U> Into<U> for Twhere
U: From<T>,

impl<T, U> TryFrom<U> for Twhere
U: Into<T>,

impl<T, U> TryInto<U> for Twhere
U: TryFrom<T>,