pub struct SENS { /* private fields */ }
Expand description
SENS Peripheral
Implementations§
Source§impl SENS
impl SENS
Sourcepub const PTR: *const RegisterBlock = {0xc800 as *const sens::RegisterBlock}
pub const PTR: *const RegisterBlock = {0xc800 as *const sens::RegisterBlock}
Pointer to the register block
Sourcepub const fn ptr() -> *const RegisterBlock
pub const fn ptr() -> *const RegisterBlock
Return the pointer to the register block
Sourcepub unsafe fn steal() -> Self
pub unsafe fn steal() -> Self
Steal an instance of this peripheral
§Safety
Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.
Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.
Methods from Deref<Target = RegisterBlock>§
Sourcepub fn sar_slave_addr1(&self) -> &SAR_SLAVE_ADDR1
pub fn sar_slave_addr1(&self) -> &SAR_SLAVE_ADDR1
0x40 - Configure slave addresses 0-1 of RTC I2C
Sourcepub fn sar_slave_addr2(&self) -> &SAR_SLAVE_ADDR2
pub fn sar_slave_addr2(&self) -> &SAR_SLAVE_ADDR2
0x44 - Configure slave addresses 2-3 of RTC I2C
Sourcepub fn sar_slave_addr3(&self) -> &SAR_SLAVE_ADDR3
pub fn sar_slave_addr3(&self) -> &SAR_SLAVE_ADDR3
0x48 - Configure slave addresses 4-5 of RTC I2C
Sourcepub fn sar_slave_addr4(&self) -> &SAR_SLAVE_ADDR4
pub fn sar_slave_addr4(&self) -> &SAR_SLAVE_ADDR4
0x4c - Configure slave addresses 6-7 of RTC I2C
Sourcepub fn sar_i2c_ctrl(&self) -> &SAR_I2C_CTRL
pub fn sar_i2c_ctrl(&self) -> &SAR_I2C_CTRL
0x58 - Configure RTC I2C transmission
Sourcepub fn sar_cocpu_int_raw(&self) -> &SAR_COCPU_INT_RAW
pub fn sar_cocpu_int_raw(&self) -> &SAR_COCPU_INT_RAW
0x128 - Interrupt raw bit of ULP-RISCV
Sourcepub fn sar_cocpu_int_ena(&self) -> &SAR_COCPU_INT_ENA
pub fn sar_cocpu_int_ena(&self) -> &SAR_COCPU_INT_ENA
0x12c - Interrupt enable bit of ULP-RISCV
Sourcepub fn sar_cocpu_int_st(&self) -> &SAR_COCPU_INT_ST
pub fn sar_cocpu_int_st(&self) -> &SAR_COCPU_INT_ST
0x130 - Interrupt status bit of ULP-RISCV
Sourcepub fn sar_cocpu_int_clr(&self) -> &SAR_COCPU_INT_CLR
pub fn sar_cocpu_int_clr(&self) -> &SAR_COCPU_INT_CLR
0x134 - Interrupt clear bit of ULP-RISCV