Struct esp32s2_hal::peripherals::UHCI0

pub struct UHCI0 { /* private fields */ }

Implementations

impl UHCI0

pub unsafe fn steal() -> UHCI0

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: *const <UHCI0 as Deref>::Target = {0x3f414000 as *const <esp32s2::UHCI0 as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <UHCI0 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn conf0(&self) -> &Reg<CONF0_SPEC>

0x00 - UHCI configuration register

pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>

0x04 - Raw interrupt status

pub fn int_st(&self) -> &Reg<INT_ST_SPEC>

0x08 - Masked interrupt status

pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>

0x0c - Interrupt enable bits

pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>

0x10 - Interrupt clear bits

pub fn dma_out_status(&self) -> &Reg<DMA_OUT_STATUS_SPEC>

0x14 - DMA data-output status register

pub fn dma_out_push(&self) -> &Reg<DMA_OUT_PUSH_SPEC>

0x18 - Push control register of TX FIFO

pub fn dma_in_status(&self) -> &Reg<DMA_IN_STATUS_SPEC>

0x1c - UHCI data-input status register

pub fn dma_in_pop(&self) -> &Reg<DMA_IN_POP_SPEC>

0x20 - Pop control register of RX FIFO

pub fn dma_out_link(&self) -> &Reg<DMA_OUT_LINK_SPEC>

0x24 - Link descriptor address and control

pub fn dma_in_link(&self) -> &Reg<DMA_IN_LINK_SPEC>

0x28 - Link descriptor address and control

pub fn conf1(&self) -> &Reg<CONF1_SPEC>

0x2c - UHCI configuration register

pub fn state0(&self) -> &Reg<STATE0_SPEC>

0x30 - UHCI decoder status register

pub fn state1(&self) -> &Reg<STATE1_SPEC>

0x34 - UHCI encoder status register

pub fn dma_out_eof_des_addr(&self) -> &Reg<DMA_OUT_EOF_DES_ADDR_SPEC>

0x38 - Outlink descriptor address when EOF occurs

pub fn dma_in_suc_eof_des_addr(&self) -> &Reg<DMA_IN_SUC_EOF_DES_ADDR_SPEC>

0x3c - Inlink descriptor address when EOF occurs

pub fn dma_in_err_eof_des_addr(&self) -> &Reg<DMA_IN_ERR_EOF_DES_ADDR_SPEC>

0x40 - Inlink descriptor address when errors occur

pub fn dma_out_eof_bfr_des_addr(&self) -> &Reg<DMA_OUT_EOF_BFR_DES_ADDR_SPEC>

0x44 - Outlink descriptor address before the last transmit descriptor

pub fn ahb_test(&self) -> &Reg<AHB_TEST_SPEC>

0x48 - AHB test register

pub fn dma_in_dscr(&self) -> &Reg<DMA_IN_DSCR_SPEC>

0x4c - The third word of the next receive descriptor

pub fn dma_in_dscr_bf0(&self) -> &Reg<DMA_IN_DSCR_BF0_SPEC>

0x50 - The third word of current receive descriptor

pub fn dma_out_dscr(&self) -> &Reg<DMA_OUT_DSCR_SPEC>

0x58 - The third word of the next transmit descriptor

pub fn dma_out_dscr_bf0(&self) -> &Reg<DMA_OUT_DSCR_BF0_SPEC>

0x5c - The third word of current transmit descriptor

pub fn escape_conf(&self) -> &Reg<ESCAPE_CONF_SPEC>

0x64 - Escape character configuration

pub fn hung_conf(&self) -> &Reg<HUNG_CONF_SPEC>

0x68 - Timeout configuration

pub fn rx_head(&self) -> &Reg<RX_HEAD_SPEC>

0x70 - UHCI packet header register

pub fn quick_sent(&self) -> &Reg<QUICK_SENT_SPEC>

0x74 - UHCI quick_sent configuration register

pub fn q0_word0(&self) -> &Reg<Q0_WORD0_SPEC>

0x78 - Q0_WORD0 quick_sent register

pub fn q0_word1(&self) -> &Reg<Q0_WORD1_SPEC>

0x7c - Q0_WORD1 quick_sent register

pub fn q1_word0(&self) -> &Reg<Q1_WORD0_SPEC>

0x80 - Q1_WORD0 quick_sent register

pub fn q1_word1(&self) -> &Reg<Q1_WORD1_SPEC>

0x84 - Q1_WORD1 quick_sent register

pub fn q2_word0(&self) -> &Reg<Q2_WORD0_SPEC>

0x88 - Q2_WORD0 quick_sent register

pub fn q2_word1(&self) -> &Reg<Q2_WORD1_SPEC>

0x8c - Q2_WORD1 quick_sent register

pub fn q3_word0(&self) -> &Reg<Q3_WORD0_SPEC>

0x90 - Q3_WORD0 quick_sent register

pub fn q3_word1(&self) -> &Reg<Q3_WORD1_SPEC>

0x94 - Q3_WORD1 quick_sent register

pub fn q4_word0(&self) -> &Reg<Q4_WORD0_SPEC>

0x98 - Q4_WORD0 quick_sent register

pub fn q4_word1(&self) -> &Reg<Q4_WORD1_SPEC>

0x9c - Q4_WORD1 quick_sent register

pub fn q5_word0(&self) -> &Reg<Q5_WORD0_SPEC>

0xa0 - Q5_WORD0 quick_sent register

pub fn q5_word1(&self) -> &Reg<Q5_WORD1_SPEC>

0xa4 - Q5_WORD1 quick_sent register

pub fn q6_word0(&self) -> &Reg<Q6_WORD0_SPEC>

0xa8 - Q6_WORD0 quick_sent register

pub fn q6_word1(&self) -> &Reg<Q6_WORD1_SPEC>

0xac - Q6_WORD1 quick_sent register

pub fn esc_conf0(&self) -> &Reg<ESC_CONF0_SPEC>

0xb0 - Escape sequence configuration register 0

pub fn esc_conf1(&self) -> &Reg<ESC_CONF1_SPEC>

0xb4 - Escape sequence configuration register 1

pub fn esc_conf2(&self) -> &Reg<ESC_CONF2_SPEC>

0xb8 - Escape sequence configuration register 2

pub fn esc_conf3(&self) -> &Reg<ESC_CONF3_SPEC>

0xbc - Escape sequence configuration register 3

pub fn pkt_thres(&self) -> &Reg<PKT_THRES_SPEC>

0xc0 - Configure register for packet length

pub fn date(&self) -> &Reg<DATE_SPEC>

0xfc - UHCI version control register

Trait Implementations

impl Debug for UHCI0

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for UHCI0

type Target = <UHCI0 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<UHCI0 as Deref>::Target

Dereferences the value.

impl DerefMut for UHCI0

fn deref_mut(&mut self) -> &mut <UHCI0 as Deref>::Target

Mutably dereferences the value.

impl Peripheral for UHCI0

type P = UHCI0

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <UHCI0 as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.