Struct esp32s2_hal::peripherals::SYSTEM
source · pub struct SYSTEM { /* private fields */ }
Implementations§
source§impl SYSTEM
impl SYSTEM
sourcepub unsafe fn steal() -> SYSTEM
pub unsafe fn steal() -> SYSTEM
Unsafely create an instance of this peripheral out of thin air.
§Safety
You must ensure that you’re only using one instance of this type at a time.
Methods from Deref<Target = RegisterBlock>§
sourcepub fn rom_ctrl_0(&self) -> &Reg<ROM_CTRL_0_SPEC>
pub fn rom_ctrl_0(&self) -> &Reg<ROM_CTRL_0_SPEC>
0x00 - System ROM configuration register 0
sourcepub fn rom_ctrl_1(&self) -> &Reg<ROM_CTRL_1_SPEC>
pub fn rom_ctrl_1(&self) -> &Reg<ROM_CTRL_1_SPEC>
0x04 - System ROM configuration register 1
sourcepub fn sram_ctrl_0(&self) -> &Reg<SRAM_CTRL_0_SPEC>
pub fn sram_ctrl_0(&self) -> &Reg<SRAM_CTRL_0_SPEC>
0x08 - System SRAM configuration register 0
sourcepub fn sram_ctrl_1(&self) -> &Reg<SRAM_CTRL_1_SPEC>
pub fn sram_ctrl_1(&self) -> &Reg<SRAM_CTRL_1_SPEC>
0x0c - System SRAM configuration register 1
sourcepub fn cpu_peri_clk_en(&self) -> &Reg<CPU_PERI_CLK_EN_SPEC>
pub fn cpu_peri_clk_en(&self) -> &Reg<CPU_PERI_CLK_EN_SPEC>
0x10 - CPU peripheral clock enable register
sourcepub fn cpu_peri_rst_en(&self) -> &Reg<CPU_PERI_RST_EN_SPEC>
pub fn cpu_peri_rst_en(&self) -> &Reg<CPU_PERI_RST_EN_SPEC>
0x14 - CPU peripheral reset register
sourcepub fn cpu_per_conf(&self) -> &Reg<CPU_PER_CONF_SPEC>
pub fn cpu_per_conf(&self) -> &Reg<CPU_PER_CONF_SPEC>
0x18 - CPU peripheral clock configuration register
sourcepub fn jtag_ctrl_0(&self) -> &Reg<JTAG_CTRL_0_SPEC>
pub fn jtag_ctrl_0(&self) -> &Reg<JTAG_CTRL_0_SPEC>
0x1c - JTAG configuration register 0
sourcepub fn jtag_ctrl_1(&self) -> &Reg<JTAG_CTRL_1_SPEC>
pub fn jtag_ctrl_1(&self) -> &Reg<JTAG_CTRL_1_SPEC>
0x20 - JTAG configuration register 1
sourcepub fn jtag_ctrl_2(&self) -> &Reg<JTAG_CTRL_2_SPEC>
pub fn jtag_ctrl_2(&self) -> &Reg<JTAG_CTRL_2_SPEC>
0x24 - JTAG configuration register 2
sourcepub fn jtag_ctrl_3(&self) -> &Reg<JTAG_CTRL_3_SPEC>
pub fn jtag_ctrl_3(&self) -> &Reg<JTAG_CTRL_3_SPEC>
0x28 - JTAG configuration register 3
sourcepub fn jtag_ctrl_4(&self) -> &Reg<JTAG_CTRL_4_SPEC>
pub fn jtag_ctrl_4(&self) -> &Reg<JTAG_CTRL_4_SPEC>
0x2c - JTAG configuration register 4
sourcepub fn jtag_ctrl_5(&self) -> &Reg<JTAG_CTRL_5_SPEC>
pub fn jtag_ctrl_5(&self) -> &Reg<JTAG_CTRL_5_SPEC>
0x30 - JTAG configuration register 5
sourcepub fn jtag_ctrl_6(&self) -> &Reg<JTAG_CTRL_6_SPEC>
pub fn jtag_ctrl_6(&self) -> &Reg<JTAG_CTRL_6_SPEC>
0x34 - JTAG configuration register 6
sourcepub fn jtag_ctrl_7(&self) -> &Reg<JTAG_CTRL_7_SPEC>
pub fn jtag_ctrl_7(&self) -> &Reg<JTAG_CTRL_7_SPEC>
0x38 - JTAG configuration register 7
sourcepub fn mem_pd_mask(&self) -> &Reg<MEM_PD_MASK_SPEC>
pub fn mem_pd_mask(&self) -> &Reg<MEM_PD_MASK_SPEC>
0x3c - Memory power-related controlling register (under low-sleep)
sourcepub fn perip_clk_en0(&self) -> &Reg<PERIP_CLK_EN0_SPEC>
pub fn perip_clk_en0(&self) -> &Reg<PERIP_CLK_EN0_SPEC>
0x40 - System peripheral clock (for hardware accelerators) enable register
sourcepub fn perip_clk_en1(&self) -> &Reg<PERIP_CLK_EN1_SPEC>
pub fn perip_clk_en1(&self) -> &Reg<PERIP_CLK_EN1_SPEC>
0x44 - System peripheral clock (for hardware accelerators) enable register 1
sourcepub fn perip_rst_en0(&self) -> &Reg<PERIP_RST_EN0_SPEC>
pub fn perip_rst_en0(&self) -> &Reg<PERIP_RST_EN0_SPEC>
0x48 - System peripheral (hardware accelerators) reset register 0
sourcepub fn perip_rst_en1(&self) -> &Reg<PERIP_RST_EN1_SPEC>
pub fn perip_rst_en1(&self) -> &Reg<PERIP_RST_EN1_SPEC>
0x4c - System peripheral (hardware accelerators) reset register 1
sourcepub fn lpck_div_int(&self) -> &Reg<LPCK_DIV_INT_SPEC>
pub fn lpck_div_int(&self) -> &Reg<LPCK_DIV_INT_SPEC>
0x50 - Low power clock divider integer register
sourcepub fn bt_lpck_div_frac(&self) -> &Reg<BT_LPCK_DIV_FRAC_SPEC>
pub fn bt_lpck_div_frac(&self) -> &Reg<BT_LPCK_DIV_FRAC_SPEC>
0x54 - Divider fraction configuration register for low-power clock
sourcepub fn cpu_intr_from_cpu_0(&self) -> &Reg<CPU_INTR_FROM_CPU_0_SPEC>
pub fn cpu_intr_from_cpu_0(&self) -> &Reg<CPU_INTR_FROM_CPU_0_SPEC>
0x58 - CPU interrupt controlling register 0
sourcepub fn cpu_intr_from_cpu_1(&self) -> &Reg<CPU_INTR_FROM_CPU_1_SPEC>
pub fn cpu_intr_from_cpu_1(&self) -> &Reg<CPU_INTR_FROM_CPU_1_SPEC>
0x5c - CPU interrupt controlling register 1
sourcepub fn cpu_intr_from_cpu_2(&self) -> &Reg<CPU_INTR_FROM_CPU_2_SPEC>
pub fn cpu_intr_from_cpu_2(&self) -> &Reg<CPU_INTR_FROM_CPU_2_SPEC>
0x60 - CPU interrupt controlling register 2
sourcepub fn cpu_intr_from_cpu_3(&self) -> &Reg<CPU_INTR_FROM_CPU_3_SPEC>
pub fn cpu_intr_from_cpu_3(&self) -> &Reg<CPU_INTR_FROM_CPU_3_SPEC>
0x64 - CPU interrupt controlling register 3
sourcepub fn rsa_pd_ctrl(&self) -> &Reg<RSA_PD_CTRL_SPEC>
pub fn rsa_pd_ctrl(&self) -> &Reg<RSA_PD_CTRL_SPEC>
0x68 - RSA memory remapping register
sourcepub fn bustoextmem_ena(&self) -> &Reg<BUSTOEXTMEM_ENA_SPEC>
pub fn bustoextmem_ena(&self) -> &Reg<BUSTOEXTMEM_ENA_SPEC>
0x6c - EDMA enable register
sourcepub fn cache_control(&self) -> &Reg<CACHE_CONTROL_SPEC>
pub fn cache_control(&self) -> &Reg<CACHE_CONTROL_SPEC>
0x70 - Cache control register
sourcepub fn external_device_encrypt_decrypt_control(
&self
) -> &Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC>
pub fn external_device_encrypt_decrypt_control( &self ) -> &Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC>
0x74 - External memory encrypt and decrypt controlling register
sourcepub fn rtc_fastmem_config(&self) -> &Reg<RTC_FASTMEM_CONFIG_SPEC>
pub fn rtc_fastmem_config(&self) -> &Reg<RTC_FASTMEM_CONFIG_SPEC>
0x78 - RTC fast memory configuration register
sourcepub fn rtc_fastmem_crc(&self) -> &Reg<RTC_FASTMEM_CRC_SPEC>
pub fn rtc_fastmem_crc(&self) -> &Reg<RTC_FASTMEM_CRC_SPEC>
0x7c - RTC fast memory CRC controlling register
sourcepub fn redundant_eco_ctrl(&self) -> &Reg<REDUNDANT_ECO_CTRL_SPEC>
pub fn redundant_eco_ctrl(&self) -> &Reg<REDUNDANT_ECO_CTRL_SPEC>
0x80 - Redundant ECO control register
sourcepub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
0x84 - Clock gate control register
sourcepub fn sram_ctrl_2(&self) -> &Reg<SRAM_CTRL_2_SPEC>
pub fn sram_ctrl_2(&self) -> &Reg<SRAM_CTRL_2_SPEC>
0x88 - System SRAM configuration register 2
sourcepub fn sysclk_conf(&self) -> &Reg<SYSCLK_CONF_SPEC>
pub fn sysclk_conf(&self) -> &Reg<SYSCLK_CONF_SPEC>
0x8c - SoC clock configuration register