Struct esp32s2_hal::peripherals::PMS

pub struct PMS { /* private fields */ }

Implementations

impl PMS

pub unsafe fn steal() -> PMS

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: *const <PMS as Deref>::Target = {0x3f4c1000 as *const <esp32s2::PMS as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <PMS as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn sdio_0(&self) -> &Reg<SDIO_0_SPEC>

0x00 - SDIO permission control register 0.

pub fn sdio_1(&self) -> &Reg<SDIO_1_SPEC>

0x04 - SDIO permission control register 1.

pub fn mac_dump_0(&self) -> &Reg<MAC_DUMP_0_SPEC>

0x08 - MAC dump permission control register 0.

pub fn mac_dump_1(&self) -> &Reg<MAC_DUMP_1_SPEC>

0x0c - MAC dump permission control register 1.

pub fn pro_iram0_0(&self) -> &Reg<PRO_IRAM0_0_SPEC>

0x10 - IBUS permission control register 0.

pub fn pro_iram0_1(&self) -> &Reg<PRO_IRAM0_1_SPEC>

0x14 - IBUS permission control register 1.

pub fn pro_iram0_2(&self) -> &Reg<PRO_IRAM0_2_SPEC>

0x18 - IBUS permission control register 2.

pub fn pro_iram0_3(&self) -> &Reg<PRO_IRAM0_3_SPEC>

0x1c - IBUS permission control register 3.

pub fn pro_iram0_4(&self) -> &Reg<PRO_IRAM0_4_SPEC>

0x20 - IBUS permission control register 4.

pub fn pro_iram0_5(&self) -> &Reg<PRO_IRAM0_5_SPEC>

0x24 - IBUS status register.

pub fn pro_dram0_0(&self) -> &Reg<PRO_DRAM0_0_SPEC>

0x28 - DBUS permission control register 0.

pub fn pro_dram0_1(&self) -> &Reg<PRO_DRAM0_1_SPEC>

0x2c - DBUS permission control register 1.

pub fn pro_dram0_2(&self) -> &Reg<PRO_DRAM0_2_SPEC>

0x30 - DBUS permission control register 2.

pub fn pro_dram0_3(&self) -> &Reg<PRO_DRAM0_3_SPEC>

0x34 - DBUS permission control register 3.

pub fn pro_dram0_4(&self) -> &Reg<PRO_DRAM0_4_SPEC>

0x38 - DBUS status register.

pub fn pro_dport_0(&self) -> &Reg<PRO_DPORT_0_SPEC>

0x3c - PeriBus1 permission control register 0.

pub fn pro_dport_1(&self) -> &Reg<PRO_DPORT_1_SPEC>

0x40 - PeriBus1 permission control register 1.

pub fn pro_dport_2(&self) -> &Reg<PRO_DPORT_2_SPEC>

0x44 - PeriBus1 permission control register 2.

pub fn pro_dport_3(&self) -> &Reg<PRO_DPORT_3_SPEC>

0x48 - PeriBus1 permission control register 3.

pub fn pro_dport_4(&self) -> &Reg<PRO_DPORT_4_SPEC>

0x4c - PeriBus1 permission control register 4.

pub fn pro_dport_5(&self) -> &Reg<PRO_DPORT_5_SPEC>

0x50 - PeriBus1 permission control register 5.

pub fn pro_dport_6(&self) -> &Reg<PRO_DPORT_6_SPEC>

0x54 - PeriBus1 permission control register 6.

pub fn pro_dport_7(&self) -> &Reg<PRO_DPORT_7_SPEC>

0x58 - PeriBus1 status register.

pub fn pro_ahb_0(&self) -> &Reg<PRO_AHB_0_SPEC>

0x5c - PeriBus2 permission control register 0.

pub fn pro_ahb_1(&self) -> &Reg<PRO_AHB_1_SPEC>

0x60 - PeriBus2 permission control register 1.

pub fn pro_ahb_2(&self) -> &Reg<PRO_AHB_2_SPEC>

0x64 - PeriBus2 permission control register 2.

pub fn pro_ahb_3(&self) -> &Reg<PRO_AHB_3_SPEC>

0x68 - PeriBus2 permission control register 3.

pub fn pro_ahb_4(&self) -> &Reg<PRO_AHB_4_SPEC>

0x6c - PeriBus2 status register.

pub fn pro_trace_0(&self) -> &Reg<PRO_TRACE_0_SPEC>

0x70 - Trace memory permission control register 0.

pub fn pro_trace_1(&self) -> &Reg<PRO_TRACE_1_SPEC>

0x74 - Trace memory permission control register 1.

pub fn pro_cache_0(&self) -> &Reg<PRO_CACHE_0_SPEC>

0x78 - Cache permission control register 0.

pub fn pro_cache_1(&self) -> &Reg<PRO_CACHE_1_SPEC>

0x7c - Cache permission control register 1.

pub fn pro_cache_2(&self) -> &Reg<PRO_CACHE_2_SPEC>

0x80 - Cache permission control register 2.

pub fn pro_cache_3(&self) -> &Reg<PRO_CACHE_3_SPEC>

0x84 - Icache status register.

pub fn pro_cache_4(&self) -> &Reg<PRO_CACHE_4_SPEC>

0x88 - Dcache status register.

pub fn dma_apb_i_0(&self) -> &Reg<DMA_APB_I_0_SPEC>

0x8c - Internal DMA permission control register 0.

pub fn dma_apb_i_1(&self) -> &Reg<DMA_APB_I_1_SPEC>

0x90 - Internal DMA permission control register 1.

pub fn dma_apb_i_2(&self) -> &Reg<DMA_APB_I_2_SPEC>

0x94 - Internal DMA permission control register 2.

pub fn dma_apb_i_3(&self) -> &Reg<DMA_APB_I_3_SPEC>

0x98 - Internal DMA status register.

pub fn dma_rx_i_0(&self) -> &Reg<DMA_RX_I_0_SPEC>

0x9c - RX Copy DMA permission control register 0.

pub fn dma_rx_i_1(&self) -> &Reg<DMA_RX_I_1_SPEC>

0xa0 - RX Copy DMA permission control register 1.

pub fn dma_rx_i_2(&self) -> &Reg<DMA_RX_I_2_SPEC>

0xa4 - RX Copy DMA permission control register 2.

pub fn dma_rx_i_3(&self) -> &Reg<DMA_RX_I_3_SPEC>

0xa8 - RX Copy DMA status register.

pub fn dma_tx_i_0(&self) -> &Reg<DMA_TX_I_0_SPEC>

0xac - TX Copy DMA permission control register 0.

pub fn dma_tx_i_1(&self) -> &Reg<DMA_TX_I_1_SPEC>

0xb0 - TX Copy DMA permission control register 1.

pub fn dma_tx_i_2(&self) -> &Reg<DMA_TX_I_2_SPEC>

0xb4 - TX Copy DMA permission control register 2.

pub fn dma_tx_i_3(&self) -> &Reg<DMA_TX_I_3_SPEC>

0xb8 - TX Copy DMA status register.

pub fn pro_boot_location_0(&self) -> &Reg<PRO_BOOT_LOCATION_0_SPEC>

0xbc - Boot permission control register 0.

pub fn pro_boot_location_1(&self) -> &Reg<PRO_BOOT_LOCATION_1_SPEC>

0xc0 - Boot permission control register 1.

pub fn cache_source_0(&self) -> &Reg<CACHE_SOURCE_0_SPEC>

0xc4 - Cache access permission control register 0.

pub fn cache_source_1(&self) -> &Reg<CACHE_SOURCE_1_SPEC>

0xc8 - Cache access permission control register 1.

pub fn apb_peripheral_0(&self) -> &Reg<APB_PERIPHERAL_0_SPEC>

0xcc - Peripheral access permission control register 0.

pub fn apb_peripheral_1(&self) -> &Reg<APB_PERIPHERAL_1_SPEC>

0xd0 - Peripheral access permission control register 1.

pub fn occupy_0(&self) -> &Reg<OCCUPY_0_SPEC>

0xd4 - Occupy permission control register 0.

pub fn occupy_1(&self) -> &Reg<OCCUPY_1_SPEC>

0xd8 - Occupy permission control register 1.

pub fn occupy_2(&self) -> &Reg<OCCUPY_2_SPEC>

0xdc - Occupy permission control register 2.

pub fn occupy_3(&self) -> &Reg<OCCUPY_3_SPEC>

0xe0 - Occupy permission control register 3.

pub fn cache_tag_access_0(&self) -> &Reg<CACHE_TAG_ACCESS_0_SPEC>

0xe4 - Cache tag permission control register 0.

pub fn cache_tag_access_1(&self) -> &Reg<CACHE_TAG_ACCESS_1_SPEC>

0xe8 - Cache tag permission control register 1.

pub fn cache_mmu_access_0(&self) -> &Reg<CACHE_MMU_ACCESS_0_SPEC>

0xec - Cache MMU permission control register 0.

pub fn cache_mmu_access_1(&self) -> &Reg<CACHE_MMU_ACCESS_1_SPEC>

0xf0 - Cache MMU permission control register 1.

pub fn apb_peripheral_intr(&self) -> &Reg<APB_PERIPHERAL_INTR_SPEC>

0xf4 - PeribBus2 permission control register.

pub fn apb_peripheral_status(&self) -> &Reg<APB_PERIPHERAL_STATUS_SPEC>

0xf8 - PeribBus2 peripheral access status register.

pub fn cpu_peripheral_intr(&self) -> &Reg<CPU_PERIPHERAL_INTR_SPEC>

0xfc - PeribBus1 permission control register.

pub fn cpu_peripheral_status(&self) -> &Reg<CPU_PERIPHERAL_STATUS_SPEC>

0x100 - PeribBus1 peripheral access status register.

pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>

0x104 - Clock gate register of permission control.

pub fn date(&self) -> &Reg<DATE_SPEC>

0xffc - Version control register.

Trait Implementations

impl Debug for PMS

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for PMS

type Target = <PMS as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<PMS as Deref>::Target

Dereferences the value.

impl DerefMut for PMS

fn deref_mut(&mut self) -> &mut <PMS as Deref>::Target

Mutably dereferences the value.

impl Peripheral for PMS

type P = PMS

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <PMS as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.