Struct esp32s2_hal::peripherals::APB_SARADC
source · pub struct APB_SARADC { /* private fields */ }
Implementations§
source§impl APB_SARADC
impl APB_SARADC
sourcepub unsafe fn steal() -> APB_SARADC
pub unsafe fn steal() -> APB_SARADC
Unsafely create an instance of this peripheral out of thin air.
§Safety
You must ensure that you’re only using one instance of this type at a time.
Methods from Deref<Target = RegisterBlock>§
sourcepub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>
pub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>
0x04 - DIG ADC common configuration
sourcepub fn fsm_wait(&self) -> &Reg<FSM_WAIT_SPEC>
pub fn fsm_wait(&self) -> &Reg<FSM_WAIT_SPEC>
0x0c - configure saradc fsm internal parameter base on test
sourcepub fn sar1_status(&self) -> &Reg<SAR1_STATUS_SPEC>
pub fn sar1_status(&self) -> &Reg<SAR1_STATUS_SPEC>
0x10 - digital adc1 status
sourcepub fn sar2_status(&self) -> &Reg<SAR2_STATUS_SPEC>
pub fn sar2_status(&self) -> &Reg<SAR2_STATUS_SPEC>
0x14 - digital adc2 status
sourcepub fn sar1_patt_tab1(&self) -> &Reg<SAR1_PATT_TAB1_SPEC>
pub fn sar1_patt_tab1(&self) -> &Reg<SAR1_PATT_TAB1_SPEC>
0x18 - item 0 ~ 3 for pattern table 1 (each item one byte)
sourcepub fn sar1_patt_tab2(&self) -> &Reg<SAR1_PATT_TAB2_SPEC>
pub fn sar1_patt_tab2(&self) -> &Reg<SAR1_PATT_TAB2_SPEC>
0x1c - Item 4 ~ 7 for pattern table 1 (each item one byte)
sourcepub fn sar1_patt_tab3(&self) -> &Reg<SAR1_PATT_TAB3_SPEC>
pub fn sar1_patt_tab3(&self) -> &Reg<SAR1_PATT_TAB3_SPEC>
0x20 - Item 8 ~ 11 for pattern table 1 (each item one byte)
sourcepub fn sar1_patt_tab4(&self) -> &Reg<SAR1_PATT_TAB4_SPEC>
pub fn sar1_patt_tab4(&self) -> &Reg<SAR1_PATT_TAB4_SPEC>
0x24 - Item 12 ~ 15 for pattern table 1 (each item one byte)
sourcepub fn sar2_patt_tab1(&self) -> &Reg<SAR2_PATT_TAB1_SPEC>
pub fn sar2_patt_tab1(&self) -> &Reg<SAR2_PATT_TAB1_SPEC>
0x28 - item 0 ~ 3 for pattern table 2 (each item one byte)
sourcepub fn sar2_patt_tab2(&self) -> &Reg<SAR2_PATT_TAB2_SPEC>
pub fn sar2_patt_tab2(&self) -> &Reg<SAR2_PATT_TAB2_SPEC>
0x2c - Item 4 ~ 7 for pattern table 2 (each item one byte)
sourcepub fn sar2_patt_tab3(&self) -> &Reg<SAR2_PATT_TAB3_SPEC>
pub fn sar2_patt_tab3(&self) -> &Reg<SAR2_PATT_TAB3_SPEC>
0x30 - Item 8 ~ 11 for pattern table 2 (each item one byte)
sourcepub fn sar2_patt_tab4(&self) -> &Reg<SAR2_PATT_TAB4_SPEC>
pub fn sar2_patt_tab4(&self) -> &Reg<SAR2_PATT_TAB4_SPEC>
0x34 - Item 12 ~ 15 for pattern table 2 (each item one byte)
sourcepub fn arb_ctrl(&self) -> &Reg<ARB_CTRL_SPEC>
pub fn arb_ctrl(&self) -> &Reg<ARB_CTRL_SPEC>
0x38 - Configure the settings of DIG ADC2 arbiter
sourcepub fn filter_ctrl(&self) -> &Reg<FILTER_CTRL_SPEC>
pub fn filter_ctrl(&self) -> &Reg<FILTER_CTRL_SPEC>
0x3c - Configure the settings of DIG ADC2 filter
sourcepub fn filter_status(&self) -> &Reg<FILTER_STATUS_SPEC>
pub fn filter_status(&self) -> &Reg<FILTER_STATUS_SPEC>
0x40 - Data status of DIG ADC2 filter
sourcepub fn thres_ctrl(&self) -> &Reg<THRES_CTRL_SPEC>
pub fn thres_ctrl(&self) -> &Reg<THRES_CTRL_SPEC>
0x44 - Configure monitor threshold for DIG ADC2
sourcepub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
0x48 - Enable DIG ADC interrupts
sourcepub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
0x4c - DIG ADC interrupt raw bits
sourcepub fn int_st(&self) -> &Reg<INT_ST_SPEC>
pub fn int_st(&self) -> &Reg<INT_ST_SPEC>
0x50 - DIG ADC interrupt status
sourcepub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
0x54 - Clear DIG ADC interrupts
sourcepub fn dma_conf(&self) -> &Reg<DMA_CONF_SPEC>
pub fn dma_conf(&self) -> &Reg<DMA_CONF_SPEC>
0x58 - Configure digital ADC DMA path
sourcepub fn clkm_conf(&self) -> &Reg<CLKM_CONF_SPEC>
pub fn clkm_conf(&self) -> &Reg<CLKM_CONF_SPEC>
0x5c - Configure DIG ADC clock
sourcepub fn apb_dac_ctrl(&self) -> &Reg<APB_DAC_CTRL_SPEC>
pub fn apb_dac_ctrl(&self) -> &Reg<APB_DAC_CTRL_SPEC>
0x60 - Configure DAC settings
sourcepub fn apb_ctrl_date(&self) -> &Reg<APB_CTRL_DATE_SPEC>
pub fn apb_ctrl_date(&self) -> &Reg<APB_CTRL_DATE_SPEC>
0x3fc - Version control register