Enum esp32s2_hal::peripherals::Interrupt
pub enum Interrupt {
Show 55 variants
WIFI_MAC,
WIFI_MAC_NMI,
WIFI_PWR,
WIFI_BB,
BT_MAC,
BT_BB,
BT_BB_NMI,
RWBT,
RWBLE,
RWBT_NMI,
RWBLE_NMI,
UHCI0,
TG0_T0_LEVEL,
TG0_T1_LEVEL,
TG0_WDT_LEVEL,
TG0_LACT_LEVEL,
TG1_T0_LEVEL,
TG1_T1_LEVEL,
TG1_WDT_LEVEL,
TG1_LACT_LEVEL,
GPIO,
GPIO_NMI,
DEDICATED_GPIO,
SPI1,
SPI2,
SPI3,
UART0,
UART1,
LEDC,
EFUSE,
TWAI,
RTC_CORE,
RMT,
PCNT,
I2C_EXT0,
I2C_EXT1,
RSA,
SHA,
AES,
SPI2_DMA,
SPI3_DMA,
TIMER1,
TIMER2,
TG0_T0_EDGE,
TG0_T1_EDGE,
TG0_WDT_EDGE,
TG0_LACT_EDGE,
TG1_T0_EDGE,
TG1_T1_EDGE,
TG1_WDT_EDGE,
TG1_LACT_EDGE,
SYSTIMER_TARGET0,
SYSTIMER_TARGET1,
SYSTIMER_TARGET2,
APB_ADC,
}
Expand description
Enumeration of all the interrupts.
Variants§
WIFI_MAC
0 - WIFI_MAC
WIFI_MAC_NMI
1 - WIFI_MAC_NMI
WIFI_PWR
2 - WIFI_PWR
WIFI_BB
3 - WIFI_BB
BT_MAC
4 - BT_MAC
BT_BB
5 - BT_BB
BT_BB_NMI
6 - BT_BB_NMI
RWBT
7 - RWBT
RWBLE
8 - RWBLE
RWBT_NMI
9 - RWBT_NMI
RWBLE_NMI
10 - RWBLE_NMI
UHCI0
13 - UHCI0
TG0_T0_LEVEL
15 - TG0_T0_LEVEL
TG0_T1_LEVEL
16 - TG0_T1_LEVEL
TG0_WDT_LEVEL
17 - TG0_WDT_LEVEL
TG0_LACT_LEVEL
18 - TG0_LACT_LEVEL
TG1_T0_LEVEL
19 - TG1_T0_LEVEL
TG1_T1_LEVEL
20 - TG1_T1_LEVEL
TG1_WDT_LEVEL
21 - TG1_WDT_LEVEL
TG1_LACT_LEVEL
22 - TG1_LACT_LEVEL
GPIO
23 - GPIO
GPIO_NMI
24 - GPIO_NMI
DEDICATED_GPIO
27 - DEDICATED_GPIO
SPI1
32 - SPI1
SPI2
33 - SPI2
SPI3
34 - SPI3
UART0
37 - UART0
UART1
38 - UART1
LEDC
45 - LEDC
EFUSE
46 - EFUSE
TWAI
47 - TWAI
RTC_CORE
49 - RTC_CORE
RMT
50 - RMT
PCNT
51 - PCNT
I2C_EXT0
52 - I2C_EXT0
I2C_EXT1
53 - I2C_EXT1
RSA
54 - RSA
SHA
55 - SHA
AES
56 - AES
SPI2_DMA
57 - SPI2_DMA
SPI3_DMA
58 - SPI3_DMA
TIMER1
60 - TIMER1
TIMER2
61 - TIMER2
TG0_T0_EDGE
62 - TG0_T0_EDGE
TG0_T1_EDGE
63 - TG0_T1_EDGE
TG0_WDT_EDGE
64 - TG0_WDT_EDGE
TG0_LACT_EDGE
65 - TG0_LACT_EDGE
TG1_T0_EDGE
66 - TG1_T0_EDGE
TG1_T1_EDGE
67 - TG1_T1_EDGE
TG1_WDT_EDGE
68 - TG1_WDT_EDGE
TG1_LACT_EDGE
69 - TG1_LACT_EDGE
SYSTIMER_TARGET0
71 - SYSTIMER_TARGET0
SYSTIMER_TARGET1
72 - SYSTIMER_TARGET1
SYSTIMER_TARGET2
73 - SYSTIMER_TARGET2
APB_ADC
89 - APB_ADC