Expand description
SPI (Serial Peripheral Interface) Controller 3
Modules§
- addr
- Address value register
- clk_
gate - SPI module clock and register clock control
- clock
- SPI clock control register
- cmd
- Command control register
- ctrl
- SPI control register
- date
- Version control
- din_
mode - SPI input delay mode configuration
- din_num
- SPI input delay number configuration
- dma_
conf - SPI DMA control register
- dma_
int_ clr - SPI interrupt clear register
- dma_
int_ ena - SPI interrupt enable register
- dma_
int_ raw - SPI interrupt raw register
- dma_
int_ set - SPI interrupt software set register
- dma_
int_ st - SPI interrupt status register
- dout_
mode - SPI output delay mode configuration
- misc
- SPI misc register
- ms_dlen
- SPI data bit length control register
- slave
- SPI slave control register
- slave1
- SPI slave control register 1
- user
- SPI USER control register
- user1
- SPI USER control register 1
- user2
- SPI USER control register 2
- w0
- SPI CPU-controlled buffer0
- w1
- SPI CPU-controlled buffer1
- w2
- SPI CPU-controlled buffer2
- w3
- SPI CPU-controlled buffer3
- w4
- SPI CPU-controlled buffer4
- w5
- SPI CPU-controlled buffer5
- w6
- SPI CPU-controlled buffer6
- w7
- SPI CPU-controlled buffer7
- w8
- SPI CPU-controlled buffer8
- w9
- SPI CPU-controlled buffer9
- w10
- SPI CPU-controlled buffer10
- w11
- SPI CPU-controlled buffer11
- w12
- SPI CPU-controlled buffer12
- w13
- SPI CPU-controlled buffer13
- w14
- SPI CPU-controlled buffer14
- w15
- SPI CPU-controlled buffer15
Structs§
- Register
Block - Register block
Type Aliases§
- ADDR
- ADDR (rw) register accessor: Address value register
- CLK_
GATE - CLK_GATE (rw) register accessor: SPI module clock and register clock control
- CLOCK
- CLOCK (rw) register accessor: SPI clock control register
- CMD
- CMD (rw) register accessor: Command control register
- CTRL
- CTRL (rw) register accessor: SPI control register
- DATE
- DATE (rw) register accessor: Version control
- DIN_
MODE - DIN_MODE (rw) register accessor: SPI input delay mode configuration
- DIN_NUM
- DIN_NUM (rw) register accessor: SPI input delay number configuration
- DMA_
CONF - DMA_CONF (rw) register accessor: SPI DMA control register
- DMA_
INT_ CLR - DMA_INT_CLR (w) register accessor: SPI interrupt clear register
- DMA_
INT_ ENA - DMA_INT_ENA (rw) register accessor: SPI interrupt enable register
- DMA_
INT_ RAW - DMA_INT_RAW (rw) register accessor: SPI interrupt raw register
- DMA_
INT_ SET - DMA_INT_SET (w) register accessor: SPI interrupt software set register
- DMA_
INT_ ST - DMA_INT_ST (r) register accessor: SPI interrupt status register
- DOUT_
MODE - DOUT_MODE (rw) register accessor: SPI output delay mode configuration
- MISC
- MISC (rw) register accessor: SPI misc register
- MS_DLEN
- MS_DLEN (rw) register accessor: SPI data bit length control register
- SLAVE
- SLAVE (rw) register accessor: SPI slave control register
- SLAVE1
- SLAVE1 (rw) register accessor: SPI slave control register 1
- USER
- USER (rw) register accessor: SPI USER control register
- USER1
- USER1 (rw) register accessor: SPI USER control register 1
- USER2
- USER2 (rw) register accessor: SPI USER control register 2
- W0
- W0 (rw) register accessor: SPI CPU-controlled buffer0
- W1
- W1 (rw) register accessor: SPI CPU-controlled buffer1
- W2
- W2 (rw) register accessor: SPI CPU-controlled buffer2
- W3
- W3 (rw) register accessor: SPI CPU-controlled buffer3
- W4
- W4 (rw) register accessor: SPI CPU-controlled buffer4
- W5
- W5 (rw) register accessor: SPI CPU-controlled buffer5
- W6
- W6 (rw) register accessor: SPI CPU-controlled buffer6
- W7
- W7 (rw) register accessor: SPI CPU-controlled buffer7
- W8
- W8 (rw) register accessor: SPI CPU-controlled buffer8
- W9
- W9 (rw) register accessor: SPI CPU-controlled buffer9
- W10
- W10 (rw) register accessor: SPI CPU-controlled buffer10
- W11
- W11 (rw) register accessor: SPI CPU-controlled buffer11
- W12
- W12 (rw) register accessor: SPI CPU-controlled buffer12
- W13
- W13 (rw) register accessor: SPI CPU-controlled buffer13
- W14
- W14 (rw) register accessor: SPI CPU-controlled buffer14
- W15
- W15 (rw) register accessor: SPI CPU-controlled buffer15